With the exponential increase in chip density and complexity has caused an increasingly serious problem of power consumption

low-power technology draw attention of designers. In the view of commonly used SOC bus do not support power management

a power management bus

providing information aware

is proposed. The salve interface of power management bus can turn clocks off and even switch the supply rail or ground off when not required

which can dramatically reduce dynamic power and static power respectively. To reduce the overhead introduced by power management bus

we design a lightweight protocol with brief and flexible operation. Whats the remarkable difference with traditional bus is its parallelism. Experimental results show the functional completeness and robustness of the compatibility.