The paper proposes an architectural design of Network Security Processor for terminal devices. This design uses macro-pipelining bus architecture

which improves the data transmitting rate of data plane and decreases the workload of bus arbitration. By introducing stream memory into the hierarchy memory architecture and using network security processor engine with optimized instruction set architecture

this design improves the ability of multi-task parallel processing. Furthermore

this design uses safe circuit to protect the processor. The results show that this design has high performance

which can meet the demand of terminal devices.