基于排序网络的大数逻辑门电路设计

孙宇; 郭靖; 朱磊

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基于排序网络的大数逻辑门电路设计

更新时间：2026-09-04

- 基于排序网络的大数逻辑门电路设计
- Design of Majority Logic Gate Circuitry Based on Sorting Networks
- 微电子学与计算机 2016年33卷第6期页码：123-125
- 作者机构：
  
  1. 1工业和信息化部电子第五研究所,广东,广州,510610
  2. 中北大学机构电子测试技术重点实验室和仪器科学与动态测试教育部重点实验室,山西,太原,030051
  3. 齐齐哈尔大学机构通信与电子工程学院,黑龙江,齐齐哈尔,160006
- 作者简介：
- 基金信息：
  
  国家自然科学基金项目 61501275
- DOI：
  中图分类号：
- 纸质出版：2016
- 稿件说明：
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孙宇, 郭靖, 朱磊. 基于排序网络的大数逻辑门电路设计[J]. 微电子学与计算机, 2016, 33(6): 123-125.

SUN Yu, GUO Jing, ZHU Lei. Design of Majority Logic Gate Circuitry Based on Sorting Networks[J]. 2016, 33(6): 123-125.
孙宇, 郭靖, 朱磊. 基于排序网络的大数逻辑门电路设计[J]. 微电子学与计算机, 2016, 33(6): 123-125. DOI：

SUN Yu, GUO Jing, ZHU Lei. Design of Majority Logic Gate Circuitry Based on Sorting Networks[J]. 2016, 33(6): 123-125. DOI：

摘要

针对传统大数逻辑门(Majority Logic Gate

MLG)高开销的问题

构造了基于排序网络的MLG电路

并以8输入的排序网络为例

使用两个4输入排序网络、四个与门以及1个或门来实现大数逻辑值.采用VerilogHDL编写代码

使用ModelSim仿真工具进行了功能验证.相比于传统的MLG

该电路可以有效地缩小45.11 %的面积、降低60.43 %的功耗和减小35.44%的延迟冗余.仿真结果表明

构造的电路可以完成正确的大数逻辑功能.

Abstract

The Majority Logic Gate (MLG) has already been used to improve the reliability of memories. As to the issue of high overheads for Majority Logic Gate

a novel MLG circuitry based on Sorting Networks is proposed. An 8-input MLG example

realized in Verilog HDL and simulated by ModelSim

has been shown to explain the structure

which includes two 4-input sorting network

four and-gates and an or-gate.Compared with the traditional MLG circuitry

the proposed circuitry can reduce 45.11% area

60.43% power

and 35.44% delay overheads respectively. The obtained results have shown that the proposed circuitry can achieve Majority Logic function rightly.

关键词

Keywords

references

Naeimi H, DeHon A. Fault secure encoder and decoder for nano memory applications[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17(4): 473-486. DOI: 473

Hughes H L, Benedetto J M. Radiation effects and hardening of MOS technology: devices and circuits[J]. IEEE Transactions on Nuclear Science, 2003, 50(3): 500-521. DOI: 500

Reviriego P, Maestro J A, Flanagan M F. Error detection in majority logic decoding of euclidean geometry low density parity check (EG-LDPC) codes[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 21(1): 156-159. DOI: 156

Baumann R C. Radiation-induced soft errors in advanced semiconductor technologies[J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3): 305-316. DOI: 305

Liu S-F, Reviriego P, Maestro J A. Efficient majority logic fault detection with difference-det codes for memory applications[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012, 20(1): 148-156. DOI: 148

Martinie S, Autran J-L, Sauze S, et al. Underground experiment and modeling of alpha emitters induced soft-error rate in CMOS 65 nm SRAM[J]. IEEE Transactions on Nuclear Science, 2012, 59(4): 1048-1053. DOI: 1048

Dodd P E, Massengill L. Basic mechanisms and modeling of single-event upset in digital microelectronics[J]. IEEE Transactions on Nuclear Science, 2003, 50(3): 583-602. DOI: 583

Lin S, Daniel J. Costello J. 差错控制编码(第2版)[M]. 北京: 机械工业出版社, 2007: 43-742. DOI: 43

Cormen T H, Leiserson C E, Rivest R L, et al. Introduction to Algorithms (第二版)[M]. 北京: 机械工业出版社, 2008: 433-442. DOI: 433

Baumann R C. Soft errors in advanced semiconductor devices—Part I: the three radiation sources[J]. IEEE Transactions on Device and Materials Reliability, 2001, 1(1): 17-22. DOI: 17

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