The breakdown voltage of Vertical Double-diffused Metal-Oxide-Semiconductor Field Transistor(VDMOS) is withstood by the PN junction form by Pbody and EPI. The cell region is designed as a abrupt junction because of the technique limitation.Field Limit Ring(FLR) is the most common structure used in termination region

and it can also take as a abrupt junction. In this paper

a 900 V termination structure is designed with the introduction of graded junction and the combination of Junction Termination Extension(JTE). The simulation breakdown voltage 992.0V with the effective termination length of only 130.2 m

and the efficiency is 98.6%. The chip area is significantly decreased

breakdown voltage is significantly increased

and the technique is the same to deep well FLRs

which means a good technique compatibility.