基于FPGA的ECC快速算法研究及设计

陈俊杰; 孟李林; 袁阳

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基于FPGA的ECC快速算法研究及设计

更新时间：2026-09-04

- 基于FPGA的ECC快速算法研究及设计
- The Research and Design of ECC Fast Algorithm Based on FPGA
- 微电子学与计算机 2016年33卷第8期页码：139-143
- 作者机构：
  
  西安邮电大学机构陕西省通信专用集成电路设计工程技术研究中心,陕西,西安,710061
- 作者简介：
- 基金信息：
  
  西安邮电大学研究生创新基金 ZL2013-27
- DOI：
  中图分类号：
- 纸质出版：2016
- 稿件说明：
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陈俊杰, 孟李林, 袁阳. 基于FPGA的ECC快速算法研究及设计[J]. 微电子学与计算机, 2016, 33(8): 139-143, 148.

CHEN Jun-jie, MENG Li-lin, YUAN Yang. The Research and Design of ECC Fast Algorithm Based on FPGA[J]. 2016, 33(8): 139-143.
陈俊杰, 孟李林, 袁阳. 基于FPGA的ECC快速算法研究及设计[J]. 微电子学与计算机, 2016, 33(8): 139-143, 148. DOI：

CHEN Jun-jie, MENG Li-lin, YUAN Yang. The Research and Design of ECC Fast Algorithm Based on FPGA[J]. 2016, 33(8): 139-143. DOI：

摘要

椭圆曲线算法(ECC)的核心是点乘算法(KP)

KP性能决定了ECC的性能.针对素数域点乘运算速度慢的问题

提出了一种基于改进NAF的点乘并行调度算法.在深入分析Jacobian射影坐标系下点加算法和倍点算法的基础上

分别设计了点加并行运算算法和倍点并行运算算法.基于Cyclone IV系列的FPGA开发平台实现了改进后ECC算法的硬件设计.硬件测试结果表明: 完成一次点乘运算需要111 860个时钟周期.与改进前算法相比

运算速度提高了40.3%.如将改进后的点乘算法基于ASIC实现

预估点乘算法性能可达到72 393.6次/s.

Abstract

The core of elliptic curve cryptographic algorithm (ECC) is the point multiplication algorithm(KP)

the performance of the KP determines the performance of the ECC. A new KP parallel scheduling algorithms based on improved NAF is presented in this paper for solving the problem of low speed of KP in prime finite field. By deeply analysing the point addition algorithm and the point doubling algorithm of the Jacobian projective coordinates

designed the point-addition parallel computing algorithm and the point-doubling parallel computing algorithm.The hardware design of the improved algorithm of ECC has completed based on the FPGA development platform of Cyclone IV family.The testing result of hardware shows that a point multiplication operation needs 111

860 clock cycles. Comparing with the previous algorithms

the computing speed improve 40.3%. If the improved algorithm is implemented based on ASIC

estimating the performance of point multiplication algorithm can reach 72

393.6 times/s.

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references

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