In this paper it presents a 10 bits 10-MS/s successive approximation register analog-to-digital converter that use a monotonic capacitor switching procedure

a new layout algorithm is adopted to reduce the mismatch in the capacitor array. It lows the power by Signal sampling on the plus of capacitor and optimal capacitor switching logic. And a low kick-back noise latch is proposed in the design of comparator. At last

optimizing the parasitic parameters of each part circuits in the layout of SAR ADC. The chip was fabricated using SMIC 0.18 m CMOS technology with1.8V supply

the10 bit 10 MS/s SAR ADC achieves SNDR of 59.0 dB and the ENOB is 9.5 bits in the post-simulation. The ADC core occupies an active area of 0.6 mm.