高性能LDPC编码器IP核设计与验证

刘艳欢; 崔文朋; 张一山; 朱曦阳; 郑哲

Chinese

您当前的位置：

首页 >

文章列表页 >

高性能LDPC编码器IP核设计与验证

更新时间：2026-09-04

- 高性能LDPC编码器IP核设计与验证
- Design and Verification of High-performance LDPC Encoder IP Core
- 微电子学与计算机 2017年34卷第4期页码：8-12
- 作者机构：
  
  1. 清华大学微电子学研究所,北京,100084
  2. 全球能源互联网研究院信息与通信研究所,北京,102211
- 作者简介：
- 基金信息：
  
  国家电网公司科技项目 SGRIDGKJ2013209号
- DOI：
  中图分类号：
- 纸质出版：2017
- 稿件说明：
移动端阅览
刘艳欢, 崔文朋, 张一山, 朱曦阳, 郑哲. 高性能LDPC编码器IP核设计与验证[J]. 微电子学与计算机, 2017, 34(4): 8-12.

LIU Yan-huan, CUI Wen-peng, ZHANG Yi-shan, et al. Design and Verification of High-performance LDPC Encoder IP Core[J]. 2017, 34(4): 8-12.
刘艳欢, 崔文朋, 张一山, 朱曦阳, 郑哲. 高性能LDPC编码器IP核设计与验证[J]. 微电子学与计算机, 2017, 34(4): 8-12. DOI：

LIU Yan-huan, CUI Wen-peng, ZHANG Yi-shan, et al. Design and Verification of High-performance LDPC Encoder IP Core[J]. 2017, 34(4): 8-12. DOI：

摘要

为了实现大数据时代以固态硬盘为代表的大容量高吞吐率存储器的纠错编码

基于数学特性优异的LDPC码

提出了一种半并行的LDPC编码器架构.采用SIMD指令的调度控制流方式实现了RU编码算法

完成了码率和码长等参数可动态配置的LDPC编码器的电路设计.通过Matlab与ModelSim联合仿真

并在Xilinx FPGA平台上验证了编码器的功能正确性.结果表明: 工作频率为100 MHz时

配置时间少于7 s且相对于其它编码器结构可以在较少的资源下吞吐率可达4.82 Gb/s.

Abstract

A semi-parallel LDPC encoder architecture was proposed for Error correction coding used in a solid state hard drive (SSD) which is the representative of large capacity and high throughput memory based on the mathematical characteristics of excellent LDPC codes. Then SIMD instruction scheduling control flow approach was applied to achieve the RU coding algorithm; LDPC encoder whose parameters such as bit rate and code length were dynamically configurable was designed. The correctness of the encoder was verified through Xilinx FPGA platform and co-simulation of Matlab and ModelSim; Tests showed that configuration time was less than 7 us and the encoder achieved a throughput of 4.82 Gb/s using fewer resources compared with other encoders when the operating frequency is 100 MHZ.

关键词

Keywords

references

Sun X R, Zeng Z, Yang Z. A novel low complexity LDPC encoder based on optimized RU algorithm with backtracking[C]//Multimedia Technology (I, CMT), 2010 International Conference on. Ningbo, China, IEEE, 2010: 1-4.

Richardson T J, Urbanke R L. Efficient encoding of low-density parity-check codes[J]. Information Theory, IEEE Transactions on, 2001, 47(2): 638-656. DOI: 638

Lee D U, Luk W, Wang C, et al. A flexible hardware encoder for low-density parity-check codes[C]//12th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004. USA, Napa, 2004: 20-23.

Kopparthi S, Gruenbacher D M. Implementation of a flexible encoder for structured low-density parity-check codes[C]//Communications, Computers and Signal Processing, IEEE Pacific Rim Conference. Victoria, Canada, 2007: 438-441.

Yoo H, Lee Y, Park I C. 7.3 Gb/s universal BCH encoder and decoder for SSD controllers[C]//Design Automation Conference (ASP-DAC), 2014. Asia and South Pacific, IEEE, 2014: 37-38.

赵明, 李亮. 在线可编程QC-LDPC码高速编码器结构[J]. 清华大学学报(自然科学版), 2009, 49(7): 1041-1044. DOI: 1041

浏览量

下载量

CSCD

文章被引用时，请邮件提醒。

提交

工具集

关联资源

低时延低复杂度QC-LDPC编码技术

基于DVB-S2协议的LDPC码译码算法研究

基于电力线通信的LDPC码分层译码算法研究

一种高效的多码率LDPC译码器的设计

大模型发展综述：从BERT到Deepseek的技术演进