中国科学院 机构 微电子研究所,北京,100029
纸质出版:2016
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刘冰燕, 蔡江铮, 黑勇. 应用于超低电压下的SRAM存储单元设计[J]. 微电子学与计算机, 2016, 33(9): 15-18, 23.
LIU Bing-yan, CAI Jiang-zheng, HEI Yong. A SRAM Bitcell Design for Ultra-Low Supply Application[J]. 2016, 33(9): 15-18.
提出一种能够工作在低电压下的SRAM存储单元
单元采用8T结构
在传统6T结构的基础上增加两个串联的NMOS构成读出端口
传统6T结构中背靠背反相器采用高阈值晶体管.采用Smic130 nm工艺仿真结果显示
提出的8T结构能够在最低0.3 V下正常操作
单元的读写噪声容限
保持噪声容限
相比传统6管结构显著提升
并且低电压下静态功耗方面均比传统6管结构降低60%~70%.
This paper presents a novel SRAM bitcell structure which is applied for ultra-low voltage. The bitcell is composed of 8 transistors
two additional NMOS transistors in series is added to traditional 6T structure as a read out port. Besides
the back to back to inverter is designed by high threshold voltage transistors. Simulations in simic 130 nm process are operated. The simulation results show that the hold and read static noise margin of proposed bitcell have enhanced greatly comparing to conventional 6T
additionally
this new bitcell can operate correctly in ultra-low voltage region. Comparing to conventional 6T cell
the static power consuming of this bitcell is reduced by 60%~70% in low voltage region.
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