基于28 nm CMOS工艺的鉴频鉴相器和电荷泵设计

谢灿; 黄水龙

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基于28 nm CMOS工艺的鉴频鉴相器和电荷泵设计

更新时间：2026-09-04

- 基于28 nm CMOS工艺的鉴频鉴相器和电荷泵设计
- The Design of Phase Frequency Detector and Charge Pump Based on 28 nm CMOS Process
- 微电子学与计算机 2016年33卷第12期页码：57-61
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 新一代通信射频芯片技术北京市重点实验室,北京,100029
- 作者简介：
- 基金信息：
  
  国家科技重大专项02专项 2014ZX02302002
- DOI：
  中图分类号：
- 纸质出版：2016
- 稿件说明：
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谢灿, 黄水龙. 基于28 nm CMOS工艺的鉴频鉴相器和电荷泵设计[J]. 微电子学与计算机, 2016, 33(12): 57-61.

XIE Can, HUANG Shui-long. The Design of Phase Frequency Detector and Charge Pump Based on 28 nm CMOS Process[J]. 2016, 33(12): 57-61.
谢灿, 黄水龙. 基于28 nm CMOS工艺的鉴频鉴相器和电荷泵设计[J]. 微电子学与计算机, 2016, 33(12): 57-61. DOI：

XIE Can, HUANG Shui-long. The Design of Phase Frequency Detector and Charge Pump Based on 28 nm CMOS Process[J]. 2016, 33(12): 57-61. DOI：

摘要

基于SMIC 28 nm CMOS工艺

完成了高性能鉴频鉴相器和电荷泵的设计.采用D触发器型鉴频鉴相器结构

通过优化其门电路结构

获得了一种两路输出信号具有良好匹配性能的鉴频鉴相器.采用源极开关的电荷泵结构

同时在该结构中采用轨到轨输入级的运放

获得了一种在较大的输出电压范围内都具有低失配电流的电荷泵.

Abstract

The design of high-performance Phase Frequency Detector and Charge Pump based on SMIC 28 nm CMOS process has been achieved in this paper. By using D flip-flop PFD and optimizing structure of the gate

a PFD has been accomplished

which two output had a good matching performance. To obtain a CP with low mismatch current under the larger range of output voltage

source-switch CP structure and an operational amplifier with a rail-to-rail input stage were used.

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references

Tsai K H, Wu J H, Liu S J. Frequency dividers with enhanced locking range[C]//IEEE Radio Frequency Integrated Circuits Symposium. Atlanta, GA: IEEE, 2008: 661-664.

北京 Willy M C Sansen. Analog Design Essentials[M]. 北京: 清华大学出版社, 2007.

Yoshimura T, Iwade S, Makino H, et al. Analysis of pull-in range limit by charge pump mismatch in a linear phase locked loop[J]. EEE Trans on Circuits and Systems I: Regular Papers, 2013, 60(4): 896-907. DOI: 896

New York Roland E Best. Phase-locked loop Design, Simulation and Application[M]. New York: McGraw Hill, 2003.

Thompson I, Brennan P V. Phase noise contribution of the phase/frequency detector in a digital PLL frequency synthesizer[J]. IEEE Proceeding-Circuits Devices and Systems, 2003, 150: 1-5. DOI: 1

Hieu N T, LeeT W, Park H H. A perfectly current matched charge pump of CP-PLL for chip to chip optical link[C]//2007 Pacific Rim Conference on Lasers and Electro-Optics. Seoul: IEEE, 2007: 7-8.

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