10 GHz扩频时钟发生器的设计

胡帅帅; 周玉梅; 张锋

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10 GHz扩频时钟发生器的设计

更新时间：2026-09-04

- 10 GHz扩频时钟发生器的设计
- Design of a 10 GHz Spread Spectrum Clock Generator
- 微电子学与计算机 2016年33卷第10期页码：63-67
- 作者机构：
  
  中国科学院机构微电子研究所,北京,100029
- 作者简介：
- 基金信息：
  
  国家"八六三"高技术研究发展项目 2011AA010403国家自然科学基金项目 61474134
- DOI：
  中图分类号：
- 纸质出版：2016
- 稿件说明：
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胡帅帅, 周玉梅, 张锋. 10 GHz扩频时钟发生器的设计[J]. 微电子学与计算机, 2016, 33(10): 63-67.

HU Shuai-shuai, ZHOU Yu-mei, ZHANG Feng. Design of a 10 GHz Spread Spectrum Clock Generator[J]. 2016, 33(10): 63-67.
胡帅帅, 周玉梅, 张锋. 10 GHz扩频时钟发生器的设计[J]. 微电子学与计算机, 2016, 33(10): 63-67. DOI：

HU Shuai-shuai, ZHOU Yu-mei, ZHANG Feng. Design of a 10 GHz Spread Spectrum Clock Generator[J]. 2016, 33(10): 63-67. DOI：

摘要

扩频时钟是一种减少数字芯片电磁干扰的有效方法.它采用预设好的调制波形

在一定频率范围内对时钟信号进行频率调制.通过小数分频频率综合器和3阶ΔΣ调制器实现了一款10 GHz扩频时钟发生器.通过改变多模分频器的分频比来实现扩频的功能.此扩频时钟发生器包括一个传统的锁相环

一个数字3阶MASH 1-1-1 ΔΣ调制器和一个波形产生器.扩频时钟发生器产生下扩频5 000×10的中心频率为10 GHz的信号

调制波形为三角波

调制频率为30.525 kHz.本设计已经采用55 nm CMOS工艺流片

在1.2 V电源电压下的总功耗为20 mW.峰值降落为29.3 dB

1 MHz频偏处的相位噪声为-110 dBc/Hz.

Abstract

Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips

using a clock signal with a frequency that is intentionally swept (frequency modulated) within a certain frequency range

with a predefined modulation profile. A 10 GHz spread spectrum clock generator (SSCG) is realized by a fractional-N frequency synthesizer with a third-order delta-sigma modulator. We accomplish the spread spectrum function by changing the divider ratio. The SSCG integrates a conventional PLL

a digital 3 order MASH 1-1-1 delta-sigma modulator and an address generator. The SSCG generates clocks at 10 GHz

a 5000×10 down spread with a triangular waveform frequency modulation of 30.525 kHz. This SSCG has been fabricated in a 55nm CMOS process

and it consumes 20 mW from a supply of 1.2 V. The EMI reduction is 29.3 dB and the simulated phase noise is -110 dBc/Hz at 1 MHz offset.

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references

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王云峰, 叶青, 满家汉, 等. 3.5GHz锁相环的设计[J]. 微电子学与计算机, 2009, 26(6): 43-46. DOI: 43

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