一种双门限语音端点检测算法的ASIC实现

张羊; 姜汉钧; 王志华

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一种双门限语音端点检测算法的ASIC实现

更新时间：2026-09-04

- 一种双门限语音端点检测算法的ASIC实现
- A Double Threshold Speech Endpoint Detection Algorithm Implementation in ASIC
- 微电子学与计算机 2016年33卷第11期页码：69-73
- 作者机构：
  
  清华大学微电子所,北京,100084
- 作者简介：
- 基金信息：
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- 纸质出版：2016
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张羊, 姜汉钧, 王志华. 一种双门限语音端点检测算法的ASIC实现[J]. 微电子学与计算机, 2016, 33(11): 69-73.

ZHANG Yang, JIANG Han-jun, WANG Zhi-hua. A Double Threshold Speech Endpoint Detection Algorithm Implementation in ASIC[J]. 2016, 33(11): 69-73.
张羊, 姜汉钧, 王志华. 一种双门限语音端点检测算法的ASIC实现[J]. 微电子学与计算机, 2016, 33(11): 69-73. DOI：

ZHANG Yang, JIANG Han-jun, WANG Zhi-hua. A Double Threshold Speech Endpoint Detection Algorithm Implementation in ASIC[J]. 2016, 33(11): 69-73. DOI：

摘要

设计了一种基于短时幅度和过零率双门限判决算法的语音端点检测ASIC实现电路

采用基于异步FIFO的动态分帧和CSD编码技术大大节省了硬件资源开销

在Modelsim和FPGA上分别进行了采集的语音信号的检测验证

结果表明此算法具有硬件实现简单、资源消耗小、检测正确率高的优点.

Abstract

A kind of speech endpoint detection ASIC circuit is designed

which is based on double threshold detection algorithm of short-term magnitude and zero-crossing rate.We can greatly save the cost of hardware resourcesby usingdynamic frame partition technology based on asynchronous FIFO and CSD coding technology.We have completed the verification using the collected speech signal in Modelsim and FPGA platform respectively. The results show that this algorithm has the advantages of simple hardware implementation

low resource consumption and high detection accuracy.

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references

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周明忠, 吉立新. 基于平均幅度和加权过零率的VAD算法及其FPGA实现[J]. 信息工程大学学报, 2010, 11(6): 713-718. DOI: 713

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