1. 首都师范大学 机构 信息工程学院,北京,102248
2. 唐山现代工控技术有限公司,河北,唐山,063000
3. 北京成像技术高精尖创新中心,北京,100048
4. 电子系统可靠性技术北京市重点实验室 机构,北京,100048
纸质出版:2016
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王珍珍, 杨志涛, 王晶, 张伟功. 基于BCH算法的高速缓存纠检错方案研究[J]. 微电子学与计算机, 2016, 33(11): 124-128.
WANG Zhen-zhen, YANG Zhi-tao, WANG Jing, et al. Research of Cache Error Detection and Correction Based on BCH Algorithm[J]. 2016, 33(11): 124-128.
针对抗辐射微处理器的容错需求
特别是在高速缓存中由单粒子效应造成的多位翻转故障
设计了一种高速缓存纠检错方案
以LEON2处理器为研究平台
分别对指令Cache和数据Cache的标记存储器和数据存储器设计并行的BCH编码器和译码器
实现多达4位错误的检测.针对检测到的多位错误
利用存储层次特征
实现对故障的有效规避.以LEON2处理器为研究平台的仿真结果证明
该方案能够有效应对高速缓存中单粒子效应所引发的多位错误
并且方案的资源开销和性能开销都比较小
为未来纳米级微处理器的容错设计提供了支撑.
A solution of cache error detection and correction based on LEON2 processor was brought forward in this paper
to meet the fault tolerance requirements of radiation hardened microprocessor
especially for Multi-Bit Upset caused by single event effect in cache. Rather
parallel BCH (Bose-Chaudhuri-Hocquenghem) encoder and decoder were designed for tag memory and data memory of instruction cache and data cache
which could achieve error detection up to four bits. Also it could handle the faults effectively after checking out them. Experimental results based on LEON2 showed that this design could efficiently handle multi-bit error due to single event effect in cache
and its resource and performance overhead was acceptable
thus it would support for fault tolerance design of the future nanoscale microprocessor.
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