1. 北京理工大学信息与电子学院,北京,100081
2. 厦门理工学院 机构 光电与通信工程学院,福建,厦门,361024
纸质出版:2018
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靳翔, 闫肃, 赵洪明, 王兴华, 陈铖颖. 宽带dither技术改善ADC SFDR性能研究[J]. 微电子学与计算机, 2018, 35(3): 9-13.
JIN Xiang, YAN Su, ZHAO Hong-ming, et al. Research of Broadband Dither Technology in Pipelined ADC[J]. 2018, 35(3): 9-13.
Dither技术是一种提高模数转换器(ADC) 动态性能的有效途径.分析了dither技术改善无杂散动态范围(SFDR) 的原理
并在流水线ADC中引入宽带大幅度dither信号
从而减小微分非线性(DNL) 误差
并提高动态性能.仿真结果表明dither的加入使得ADC的SFDR从56.35dB提高到66dB
信噪比(SNR) 下降了1.05dB.
Dither technology is an effective method to improve the ADC dynamic performance.The theory of dither technology to improve the SFDR is analyzed
the broadband and large amplitude dither is applied in the pipelined ADC to reduce the DNL error and improve the dynamic performance.The simulation result show that ADCs SFDR improving from 56.35 dB to 66 dB and SNR reducing 1.05 dB.
Kikket C J, Bigdeli A. Hardware additive dither for analogue to digital converters[C]//14th Australian Microelectronics Conference. Australian, 1997, 43 (1): 156-161.
Quinn P J, Van Roermund A H M. Accuracy limitations of pipelined ADCs[J]. IEEE International Symposium on Circuits and Systems, 2005 (3): 1956-1959. DOI: 1956
Kikkert C J, Bigdeli A. Frequency shift dither for analogue to digital converters[C]//Fifth International Symposium on Signal Processing and its Applications. Seoul, Korea, 1999: 729-732.
Yun Chiu, Paul R Gray, Borivojc Nikolic. A 14b12MS/s CMOS pipeline ADC with over 100dB SFDR[J]. IEEE Journal of Solid-State Circuits, 2004, 39 (12): 2139-2151. DOI: 2139
Robert A Wannamaker, Stanley P Lipshitz, John Vanderkooy, et al. A theory of nonsubtractive dither[J]. Signal Processing IEEE Transactions on, 2000, 48 (2): 499-516. DOI: 499
陈小猛, 张羽中, 艾宪芸, 等. 数字多通道脉冲幅度分析器中数字Dither加入方法[J]. 核技术, 2015, 38 (5): 47-52. DOI: 47
丁洋, 王宗民, 周亮, 等. 一种用于16位流水线ADC的多比特子DAC电容失配校准方法[J]. 微电子学与计算机, 2012, 29 (6): 172-176. DOI: 172
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