1. 桂林电子科技大学 机构 电子工程与自动化学院,广西,桂林,541004
2. 广西自动检测技术与仪器重点实验室,广西,桂林,541004
纸质出版:2017
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许川佩, 王苏妍. 基于多种群改进量子进化算法的3D NoC测试功耗优化[J]. 微电子学与计算机, 2017, 34(8): 17-22.
XU Chuan-pei, WANG Su-yan. Optimizing Test Power Consumption in 3D NoC Based on Improved Quantum-Inspired Evolutionary Algorithm of Multi Populations[J]. 2017, 34(8): 17-22.
针对在测试过程中芯片产生较大的热效应会破坏芯片的可靠性,本文在进行测试规划获得最短测试时间的基础上,将测试时间作为约束,采用多种群改进量子进化算法优化测试功耗,以降低测试成本,防止功耗过高造成芯片不可逆的损坏.算法中,为了避免单一种群不能保证种群多样性,将多种群操作与算法相结合,并引入优体交叉策略,以提高算法的全局寻优能力.以ITC’02基准电路作为实验对象,实验结果表明,该算法能迅速收敛到最优解,缩短了测试时间,提高了测试效率,并在测试时间约束下,优化了测试功耗.
Considering that the large thermal effect produced by chips in the process of testing will damage the reliability of the chips
in this paper
a new method using improved quantum-inspired evolutionary algorithm of multi populations is proposed to optimize the test power consumption. The proposed method is meant to reduce the test cost and prevent the chip from being damaged due to excessive power consumption. In order to avoid the single population cant guarantee the diversity of populations
this paper combines multiple populations operation with algorithm and adopts the strategy of crossover in excellent individuals to improve the ability of global optimization. Taking ITC02 standard circuit as the test object
the experiment results demonstrate that the proposed method can converge to the optimal solution quickly
which can reduce the total test time and improve the test efficiency
in addition
the test power consumption is optimized under the constraint of the test time.
Cheng Y Q, Zhang L, Han Y H, et al. TSV minimization for circuit-partitioned 3D SoC test wrapper design[J]. Journal of Computer Science and Technology, 2013, 28(1): 119-128. DOI: 119
Fccro B S, Pande P P, Networks-on-Chip in a three-dimensional environment: a performance evaluation[J]. IEEE Transactions on Computers, 2009, 58(1): 32-45. DOI: 32
Cota E, Zeferion C, Kreutz M, et al. The impact of NoC reuse on the testing of core-based system[C]//VLSI TestSymposium 2003. Napa Valley, California, 2003: 128-133.
申抒含, 金炜东. 多进制概率角复合位编码量子进化算法[J]. 模式识别与人工智能, 2005, 18(6): 657-663. DOI: 657
钱洁, 郑建国, 张超群, 等. 量子进化算法研究现状综述[J]. 控制与决策, 2011, 26(3): 321-326. DOI: 321
许川佩, 赵龙. 基于改进量子进化算法的NoC测试规划研究[J]. 微电子学与计算机, 2014, 31(12): 23-27. DOI: 23
欧阳一鸣, 冯伟, 梁华国. 功耗限制下的NoC测试端口的优化选择方法[J]. 计算机应用, 2008, 28(4): 1026-1028. DOI: 1026
许川佩, 凌景. 基于ICEA的3D NoC测试规划研究[J]. 微电子学与计算机, 2016, 33(7): 74-78. DOI: 74
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