基于10Gbase-KR协议的PCS层弹性缓冲器设计

杨钞翔; 张春; 王自强; 王志军; 谢翔; 姜汉钧

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基于10Gbase-KR协议的PCS层弹性缓冲器设计

更新时间：2026-09-04

- 基于10Gbase-KR协议的PCS层弹性缓冲器设计
- Design of Elastic Buffer in Physical Coding Sublayer Based on 10 Gbase-KR
- 微电子学与计算机 2018年35卷第3期页码：14-18
- 作者机构：
  
  清华大学微电子学研究所,北京,100084
- 作者简介：
- 基金信息：
  
  国家科技重大专项 2016ZX01012101
- DOI：
  中图分类号：
- 纸质出版：2018
- 稿件说明：
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杨钞翔, 张春, 王自强, 王志军, 谢翔, 姜汉钧. 基于10Gbase-KR协议的PCS层弹性缓冲器设计[J]. 微电子学与计算机, 2018, 35(3): 14-18.

YANG Chao-xiang, ZHANG Chun, WANG Zi-qiang, et al. Design of Elastic Buffer in Physical Coding Sublayer Based on 10 Gbase-KR[J]. 2018, 35(3): 14-18.
杨钞翔, 张春, 王自强, 王志军, 谢翔, 姜汉钧. 基于10Gbase-KR协议的PCS层弹性缓冲器设计[J]. 微电子学与计算机, 2018, 35(3): 14-18. DOI：

YANG Chao-xiang, ZHANG Chun, WANG Zi-qiang, et al. Design of Elastic Buffer in Physical Coding Sublayer Based on 10 Gbase-KR[J]. 2018, 35(3): 14-18. DOI：

摘要

为了实现高速数据流的跨时钟域传输

根据万兆以太网10Gbase-KR协议设计了一款性能稳定的弹性缓冲器

并对设计进行逻辑综合和门级仿真

验证了设计的正确性.该弹性缓冲器采用常半满控制方式

深度为16

数据传输速率为10Gbps

读写时钟频率为156.25 MHz

通过检测读写地址差值变换情况来比较读写速度

并自动插入或删除IDLE字符

以此调节弹性缓冲器读写速度完成时钟频率补偿

实现了高速数据流的跨时钟域正确传输.

Abstract

An elastic buffer is designed to satisfy the need of clock domain crossing of the high-speed data flow based on the 10Gbase-KR ethernet protocol. Then the logical synthesis and gate-level simulation is conducted to demonstrate the design is correct. The elastic buffer is controlled with the normal half-full method

of which the depth is 16

the data transfer rate is 10Gbps

and the read-write clock frequency is 156.25MHz. By detecting the changes of the difference between the reading and writing address

it can make a contrast with the reading and writing speed and automatically insert or delete the IDLE characters. In the way

it can adjust the elastic buffer to realize clock frequency compensation and the clock domain crossing of the high-speed data flow correctly.

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Keywords

references

IEEE Std 802.3apTM-2007(Amendment to IEEE Std 802.3TM-2005). LAN/MAN Standards Committee of the IEEE Computer Society[S]. IEEE 3 Park Avenue, New York, USA, 2007: 1-2.

Michelogiannakis G, Balfour J, Dally W J. Elastic-buffer flow control for on-chip networks[C]// IEEE, International Symposium on High PERFORMANCE Computer Architecture. Vienna, Austria, IEEE, 2009: 151-162.

Verilog E, Cummings C E. Simulation and synthesis techniques for asynchronous FIFO design[J]. Snug, 2002, Section TB2(3): 1-18. DOI: 1

Chang H, Peng T, Ke D, et al. Design and implementation of elastic buffer for Universal Serial Bus 3.0[J]. Ieice Electronics Express, 2016, 57(5): 5-35. DOI: 5

Frazier H M. Aggregation at the physical layer[J]. IEEE Communications Magazine, 2008, 46(2): S12. DOI: S12

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