西安邮电大学 机构 电子工程学院,陕西,西安,710100
纸质出版:2018
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何星宏, 阴亚芳, 戴程. 浮点及整数混合运算器的设计与实现[J]. 微电子学与计算机, 2018, 35(2): 52-55, 60.
HE Xing-hong, YIN Ya-fang, DAI Cheng. Design and Implementation for a Integer-Float ALU[J]. 2018, 35(2): 52-55.
针对现行普遍的浮点运算器耗费面积较大
功能实现结构松散的问题
设计实现一款浮点及整数混合运算器(Mixture-Arithmetic Logic Unit
M-ALU).该运算器基于基4算法华莱士树型结构
并尝试一种新的阶码对齐方法
合并整数运算与浮点运算处理逻辑.在三级流水线结构下可准确完成单精度浮点数
扩展精度浮点数以及整数基本运算.采用基于synopsys提供的Design Compler综合工具在SMIC 65 nm工艺库下完成综合
达到500 MHz主频.
For solve the issue that commont floating pointe ALU comsumes large area and srtucture loosely
a floating point and integer mixed operator M-ALU are designed and implemented. The algorithm based on the base-4 algorithm Wallace tree structure
and try a new order code alignment method
merging integer arithmetic and floating point arithmetic processing logic. In the three-stage pipeline structure can be accurately completed single-precision floating-point
extended precision floating-point and integer basic operations. Based on the synopsys provided by the Design Compiler synthesis tool in the SMIC 65nm process library to complete the synthesis
to 500 MHz frequency.
Quinnell E, Swartzlander E E, Lemonds C. Floating-point fused multiply-add architectures[C]// Asilomar Conference on. Pacific Grove, CA, USA, IEEE Xplore, 2007: 331-337.
姜浩. 高精度可靠浮点计算及舍入误差分析研究[D]. 长沙: 国防科学技术大学, 2013.
Jacobi C, Oh H J, Tran K D, et al. The Vector floating-point unit in a sy111111ergistic processor element of a cell processor[C]// IEEE Symposium on Computer Arithmetic. Cape Cod, MA, USA, IEEE Computer Society, 2005: 59-67.
Prashanth B U V, Kumar P A, Sreenivasulu G. Design % implementation of floating point ALU on a FPGA processor[C]// Computing, Electronics and Electrical Technologies. English, Book, 2012: 772-776.
李亚民. 计算机原理与设计Verilog HDL版Computer principles and design in Verilog HDL[M]. 北京: 清华大学出版社, 2011.
Tsoumanis K, Xydis S, Efstathiou C, et al. An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator[J]. Circuits % Systems I Regular Papers IEEE Transactions on, 2014, 61(4): 1133-1143. DOI: 1133
Schmookler M S, Nowka K J. Leading zero anticipation and detection-a comparison of methods[J]. IEEE Symposium on Computer Arithmetic, 2001, 22(41): 7-12. DOI: 7
KahanElect W. IEEE Standard for Floating-Point Arithmetic[J]. Lecture Notes on the Status of IEEE 754, 2008: 1-70. DOI: 1
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