上海交通大学 电子信息与电气工程学院,上海,200240
纸质出版:2017
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金晟, 赵仲元, 绳伟光, 何卫锋. 针对粗粒度可重构处理器的通用循环编译技术[J]. 微电子学与计算机, 2017, 34(7): 42-45.
JIN Sheng, ZHAO Zhong-yuan, SHENG Wei-guang, et al. A General Loop-Compiling Technique for Course-Grained Reconfigurable Processor[J]. 2017, 34(7): 42-45.
粗粒度可重构处理器结合了高性能和高灵活性的优点
但是现有编译技术难以处理不定长循环和非完美循环.本文分别针对不定长循环和非完美循环提出了高效的编译技术
使得编译器可以处理通用形式的循环且均可以充分利用可重构处理器的计算能力.
Coarse-grained reconfigurable processor combines the advantages of high performance and high flexibility
but the existing compiler technology is difficult to deal with variable-length loops and imperfect loops. In this paper
we propose an efficient compilation technique for variable-length loops and imperfect loops
so that the compiler can deal with the general form of loops and can make full use of the reconfigurable processor computing power.
Lee J, Seo S, Lee H, et al. Flattening-based mapping of imperfect loop nests for CGRAs?[C]//Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2014 International Conference on. Jersey City, New Jersey, USA, IEEE, 2014: 1-10.
Mirsky E, DeHon A. MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources[C]//FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on. Napa Valley, California, IEEE, 1996: 157-166.
Sim H, Lee H, Seo S, et al. Mapping imperfect loops to coarse-grained reconfigurable architectures[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 35(7): 1092-1104. DOI: 1092
Hamzeh M, Shrivastava A, Vrudhula S. EPIMap: using epimorphism to map applications on CGRAs[C]//Proceedings of the 49th Annual Design Automation Conference. San Francisco, California, USA, ACM, 2012: 1284-1291.
Yin C, Yin S, Liu L, et al. Compiler framework for reconfigurable computing system[C]//Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on. IEEE, Milpitas, California, USA, 2009: 991-995.
Hamzeh M, Shrivastava A, Vrudhula S. REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs)[C]//Proceedings of the 50th Annual Design Automation Conference. San Francisco, CA, USA, ACM, 2013: 18.
Lin X, Yin S, Liu L, et al. Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures[C]//2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). Chiba, Japan, IEEE, 2016: 456-461.
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