The high-speed serial data transmission protocol JESD204B is studied and designed in order to solve the accurate transmission of high-speed AD sampling data. In the design of the interface circuit

a 8b/10b coding structure called parallel coding is adopted to reduce the burden of the system clock and improve the data transmission rate

the design of the transmitter interface circuit is completed.In this paper

we use the Arria V GT FPGA development board and QUARTUS Ⅱ static timing analysis tool to verify and analyze the structure of the design of the interface circuit and the parallel code.The experimental results show that the design of the interface circuit is correct and the performance meets the requirements of high speed data transmission. The 8b/10b coding structure can significantly improve the data transmission rate and reduce system clock requirements.