In this paper

we finish the physical design of DDR3 memory interface in a high-performance DSP chip base on 40 nm process

and the floorplan

clock tree and timing convergence method of DDR3 memory interface are proposed and implemented.In the floorplan stage

the layout size of DDR3 and the planning of macros

IO units are determined considering the factors such as area and timing.In the timing convergence stage

we analyze the clock and path structure of DDR3

and make precise manual planning for the critical path.we also realized the automation skew check script

controll the bus skew within 40 ps.The experimental results show that the design of this paper achieves the goal of frequency 533 MHz

maximum data rate 2 133 Mb/s.