Aiming at the application of low power wireless sensor in wireless sensor network

a ultra low power Successive Approximation Register Analog-to-Digital Converter (SAR ADC) has been designed. A switching logic based on Vcm-Based reference voltage is proposed to reduce the power consumption of the DAC when the reference voltage is switched. The DAC capacitor array module uses the sectional structure

the unit capacitance uses the optimized MOM capacitance

enhances the ADC matching and the precision effectively. In addition

a double tail current dynamic latch comparator is used to optimize the power consumption. The ADC is implemented in CMOS 65 nm technology. The post simulation results shown that under 1.2 V supply voltage

the sampling rate is 16 MSPS

the power consumption is 140 W

effective number of bits reached 9.42 bit

and the figure-of-merit (FOM) is 12.8 fJ/conversion-step.