This paper presents a tracking analog-to-digital converter (ADC).By reusing the quantizer

the tracking ADC no long needs subtraction and digital-to-analog (DAC) module that the conventional structure needs.This technique could decrease the power consumption and the chip area.The quantizer adopts 8-bit monotonic switching scheme successive-approximation-register (SAR) ADC.In addition

to further increase efficiency

a time domain comparator is used to replace the analog domain comparator.This ADC is simulated in a 90 nm CMOS technique.It works with 16 MHz sampling rate

8 over sampling rate (OSR).It achieves 59.6 dB SNDR for an input signal around 227 KHz with the help of a simple digital low pass filter.Counting in the filter

it consumes 28.5 W power under 1-Vsupply.The figure-of-merit (FOM) is 18.4 fJ/STEP.In addition

such topology bring us the advantage of easy design migration among technology nodes for seeking greater efficiency improvement.