一种高性能无片外电容型LDO设计

程立; 黄鲁

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一种高性能无片外电容型LDO设计

更新时间：2026-09-04

- 一种高性能无片外电容型LDO设计
- Design of a High Performance Output-Capacitorless LDO
- 微电子学与计算机 2017年34卷第10期页码：119-122
- 作者机构：
  
  中国科学技术大学电子科学与技术系,安徽,合肥,230027
- 作者简介：
- 基金信息：
- DOI：
  中图分类号：
- 纸质出版：2017
- 稿件说明：
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程立, 黄鲁. 一种高性能无片外电容型LDO设计[J]. 微电子学与计算机, 2017, 34(10): 119-122.

CHENG Li, HUANG Lu. Design of a High Performance Output-Capacitorless LDO[J]. 2017, 34(10): 119-122.
程立, 黄鲁. 一种高性能无片外电容型LDO设计[J]. 微电子学与计算机, 2017, 34(10): 119-122. DOI：

CHENG Li, HUANG Lu. Design of a High Performance Output-Capacitorless LDO[J]. 2017, 34(10): 119-122. DOI：

摘要

设计了一种高性能无片外电容型LDO线性稳压器.其中

EA采用推挽输出放大器设计

在静态时保持低功耗

瞬态响应时提供大的输出电流

提高LDO的响应速率.高环路增益使LDO电路具有很高的稳压精度; 采用零点补偿技术

保证了LDO环路稳定性.LDO采用0.13 μm CMOS工艺设计

仿真结果表明

在1.2 V~2.0 V输入电压下

LDO输出稳定的1.0 V电压

输出负载电流为50 μA~100 mA

最大负载电容可达到100 pF

低频PSR为-67.5dB@100mA~-85.5dB@50μA

负载调整率0.8μV/mA

LDO的静态电流为50 μA

整体版图面积为0.016 3 mm.

Abstract

A High Performance Output-Capacitorless LDO is presented in this paper. In this design

EA applies a push-pull output amplifier

so that it can maintain low power consumption in quiescent state

and provide large output current in the transient response

which greatly improve the response rate. High loop gain allows the LDO circuit to achieve very high regulation accuracy; and using zero compensation technology to enhance the stability of the LDO loop. The LDO is designed in 0.13 μm CMOS process. Simulation results show that the output voltage can be stable at 1.0 V when its supply is range from 1.2 V to 2.0 V. The output load current is from 50uA to 100 mA

the maximum load capacitance is up to 100 pF

PSR at low frequency is -67.5dB@100mA~-85.5dB@50μA. Load regulation is 0.8μV/mA. The LDO only consumes 50 μA quiescent current

and the overall layout area is 0.0163mm.

关键词

Keywords

references

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Man T Y, Mok P K T, Chan M. A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulatorswith transient response improvement[J]. IEEE Trans. Circuits Syst. Ⅱ, 2007, 54(9): 755-759. DOI: 755

Razavi B. 模拟CMOS集成电路设计[M]. 陈贵灿, 程军, 译. 西安: 西安交通大学出版社, 2002.

Park C J, Onabajo M, Silva-Martínez J. External capacitor-lesslow drop-out regulator with 25 dB superior power supply rejection inthe 0.4-4 MHz range[J]. IEEE J. Solid-State Circuits, 2014, 49(2): 486-501. DOI: 486

ZHAN C, KI W H, An output-capacitor-free adaptively viased low-dropout regulator with sub-threshold undershoot-reduction for SoC[J]. IEEE Trans. Circuits Syst. Ⅰ: Regu Pap, 2012, 59(5): 1119-1131. DOI: 1119

Ho E N Y, Mok P K T. Wide-loading-range fully integrated LDO with a power-supply ripple injection filter[J]. IEEE Trans. Circuits Syst. Ⅱ, 2012, 59(6): 356-360. DOI: 356

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