结合片上数据布局和数据传输效率:一种针对multi-bank CGRA的优化算法

刘延涛; 赵仲元; 绳伟光; 何卫锋

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结合片上数据布局和数据传输效率:一种针对multi-bank CGRA的优化算法

更新时间：2026-09-04

- 结合片上数据布局和数据传输效率:一种针对multi-bank CGRA的优化算法
- Joint Data Placement and Transformation: An Optimizing Algorithm for Multi-bank CGRA System
- 微电子学与计算机 2018年35卷第7期页码：13-18
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
  
  国家高技术研究发展计划 2012AA012702上海交通大学科技创新专项基金 YG2014MS70
- DOI：
  中图分类号：
- 纸质出版：2018
- 稿件说明：
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刘延涛, 赵仲元, 绳伟光, 何卫锋. 结合片上数据布局和数据传输效率:一种针对multi-bank CGRA的优化算法[J]. 微电子学与计算机, 2018, 35(7): 13-18.

LIU Yan-tao, ZHAO Zhong-yuan, SHENG Wei-guang, et al. Joint Data Placement and Transformation: An Optimizing Algorithm for Multi-bank CGRA System[J]. 2018, 35(7): 13-18.
刘延涛, 赵仲元, 绳伟光, 何卫锋. 结合片上数据布局和数据传输效率:一种针对multi-bank CGRA的优化算法[J]. 微电子学与计算机, 2018, 35(7): 13-18. DOI：

LIU Yan-tao, ZHAO Zhong-yuan, SHENG Wei-guang, et al. Joint Data Placement and Transformation: An Optimizing Algorithm for Multi-bank CGRA System[J]. 2018, 35(7): 13-18. DOI：

摘要

多bank的粗粒度可重构处理器结合了高性能和高灵活性的优点

但是现有的编译技术难以充分利用其多bank存储资源

本文在同时考虑数据放置和数据传输效率的基础上

提出了一种可以从优化整体运算性能的一种算法

并建立模型检验优化效果

结果显示

优化后的可重构处理器效率是现有优化算法的2.74倍.

Abstract

Multi-bank Coarse-grained reconfigured processor combines the advantages of high performance and high flexibility

but the existing compiler technology is difficult to make full use of the Multi-bank memory resources

this paper proposes an efficient optimizing algorithm on optimizing the data placement and efficiency of data transformation simultaneously

then we build a model to evaluate the performance

the result shows our approach is capable of optimizing the performance to 2.74x of the state-of-the-art method.

关键词

Keywords

references

Alexander Fell, Zoltan EndreRakossy, Anupam Chattopadhyay. Force-directed scheduling for data flow graph mapping on coarse-grained reconfigu-rablearchitectures[C]// ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on. IEEE, 2014: 1-8.

Bingfeng Mei, Serge Vernalde, DiederikVerkest, et al. Exploiting loop-level parallelism on coarse-grained reconfgurable architectures using modulo scheduling[C]//In Computers and Digital Techniques, IEEE Proceedings. 2003, 150: IET, 255-261.

Shouyi Yin, Zhicong Xie, Chenyue Meng, et al.Multibank memory optimization for parallel data access in multiple dataArrays[C]//2016 IEEE/ACM International Conference on Comp-uterAided Design (ICCAD). Austin, TX, 2016: 1-8.

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S Yin, Xianqing Yao, Tianyi Lu, et al. Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory[C]//2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Austin, TX, 2016: 1-8.

Ramakrishna Rau B. Iterative modulo scheduling: An algorithm for software pipelining loo-ps[C]// Proceedings of the 27th annual international symposium on Microarchitecture. ACM, 1994, 63-74.

Krste Asanovic, Ras Bodik, Bryan Christopher Catanzaro, et al. The land-scape of parallel computing research: A view from Berkeley[R]. Berkeley, EECS Department, University of California, 2006: U-CB/EECS-2006-183.

Cong J, Huang H, Ma C, et al. A fully pipelined and dynamically composable archit-ecture of CGRA[C]// 2014 IEEE 22nd Annual Intern-ational Symposium on Field-Programmable Custom Computing Machines. Boston, 2014: 9-16.

Karunaratne M, Mohite A K, Mitra T, et al. HyCUBE: A CGRA with reconfigurable single-cycle multi-hop interconnect[C]// 2017 54th ACM ED-AC/IEEE Design Automation Conference (DAC). Austin, TX, USA, 2017: 1-6.

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