The feature of block RAM in FPGA determines that asynchronous FIFO with read-write bit-width conversion is easy to waste of storage resources. To solve this problem

a new parallel FIFO architecture

multi-channel FIFO sharing multiple RAM (MFMR)

based on Storage array

is proposed in this paper. Compared with the common FIFO IP

MFMR reduces the consumption of proprietary Block RAM (BRAM) storage resource by a small amount of only a few general-purpose slice resources

and multiplies the efficient utilization of storage resources by up to N times the utilization of common FIFO IP resources

in which =max(

1/)

where is the ratio between the read-bit width and the write-bit width of the FIFO.