1. 中国科学院 上海微系统与信息技术研究所 信息功能材料国家重点实验室 机构,上海,200050
2. 上海科技大学 机构 物质科学与技术学院,上海,201210
3. 中国科学院大学 机构,北京,101408
4. 上海新储集成电路有限公司,上海,201500
纸质出版:2018
移动端阅览
黄添益, 王本艳, 景蔚亮, 宋志棠, 陈邦明. 一种采用新型逻辑算法的SAR ADC[J]. 微电子学与计算机, 2018, 35(7): 35-40.
HUANG Tian-yi, WANG Ben-yan, JING Wei-liang, et al. An SAR ADC Using A New Type of Logical Algorithm[J]. 2018, 35(7): 35-40.
基于SMIC 40nm CMOS工艺
设计了一种12位逐次逼近寄存器式模数转换器(SAR ADC).在正常工作模式的基础上
增加了当模拟输入信号变化缓慢时
锁定前4位
仅转换后8位的工作模式
降低了ADC的功耗
提高了ADC的采样率
同时分辨率保持不变.当模拟输入信号变化较大时
ADC又可重新回到正常工作模式.在1.1 V的电源电压
3.6 MS/s的采样率下
ADC总功耗为43 W
品质因数FOM为10.1fJ/(conv.·step).
A 12-bit successive-approximation-register analog-to-digital converter (SAR ADC) was designed in SMIC 40nm CMOS process. Base on traditional SAR logic
add an algorithm of when analog input signal changes slowly
ADC locking its first 4 bits
and only do last 8 conversions. And when analog input signal has great change
ADC returns to normal working mode. It decreases power consumption and increase sampling rate of ADC
but doesnt change resolution of ADC. Under a 1.1V supply and 3.6 MS/s sampling rate
the total power consumption of ADC is 43 W
and the FOM is 10.1fJ/(conv.·step).
Chang A H, Leehs Boingd. A 12b 50MS/s 2.1 mW SAR ADC with redundancy and digital background calibration[C]//IEEE ESSCIRC 2013. Bucharest, Romania, 2013: 109-112.
Zhou Y, Xu B, Chiu Y, A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration[C]//IEEE Symp. VLSI Circuits Dig. Tech. Papers, Honolulu, HI, USA, 2014: 1-2.
Lin C Y, Lee T C. A 12bit 210MS/s 5.3mW Pipelined-SAR ADC with a passive residue transfer technique[C]// IEEE Symp. VLSI Circuits Dig. Tech. Papers, Honolulu, HI, USA. 2014: 1-2.
Cheng-Hsun Ho, Soon-Jyh Chang, et al. A 3.9-fJ/cs. 0.5V 10bit 100-kS/s low power SAR ADC with time-based fixed window[C]// ISCAS, Melbourne VIC. Australia, 2014: 2345-2348.
Verma N, Chandrakasan A P. A 25μW 100 kS/s 12 bit ADC for wireless micro-sensor applications[C]//IEEE Int Sol Sta Circ Conf. San Francisco, CA, USA, 2006: 222-223.
Yao-Sheng Hu, Chi-Huai Shih, et al. A 0.6V 6.4 fJ/ conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS[C]//IEEE A-SSCC, 2014, KaoHsiung, Taiwan, 2014: 81-84.
Liu W, Huang P, Chiu Y. A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR[C]//ISSCC Dig. Tech. Papers. San Francisco, CA, USA. 2010: 380-381.
Huang C P, Lin J M, Shyu Y T, et al. A systematic design methodology of a synchronous SAR ADCs[J]. IEEE Trans VLSI Syst, 2016, 24(5): 1835-1848. DOI: 1835
Kapusta R, Shen J, Decker S, et al. A 14 b 80MS/s SAR ADC with 73.6 dB SNDR in 65 nm CMOS[J]. IEEE J Sol Sta Circ, 2013, 48(12): 3059-3065. DOI: 3059
Zhu Y, Chanc H, Sins W, et al. A 35 fJ 10 b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancelation[J]. IEEE J Sol Sta Circ, 2011, 47(11): 61-64. DOI: 61
0
浏览量
22
下载量
0
CSCD
关联资源
相关文章
相关作者
相关机构
京公网安备11010602201714号