一种基于NAND Flash的多通道存储系统编址方式研究与实现

赵倩; 唐磊

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一种基于NAND Flash的多通道存储系统编址方式研究与实现

更新时间：2026-09-04

- 一种基于NAND Flash的多通道存储系统编址方式研究与实现
- Research and Implementation of Addressing Method Based on NAND Flash Multichannel Storage System
- 微电子学与计算机 2018年35卷第9期页码：32-36
- 作者机构：
  
  西安微电子技术研究所,陕西,西安,710054
- 作者简介：
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- 纸质出版：2018
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赵倩, 唐磊. 一种基于NAND Flash的多通道存储系统编址方式研究与实现[J]. 微电子学与计算机, 2018, 35(9): 32-36.

ZHAO Qian, TANG Lei. Research and Implementation of Addressing Method Based on NAND Flash Multichannel Storage System[J]. 2018, 35(9): 32-36.
赵倩, 唐磊. 一种基于NAND Flash的多通道存储系统编址方式研究与实现[J]. 微电子学与计算机, 2018, 35(9): 32-36. DOI：

ZHAO Qian, TANG Lei. Research and Implementation of Addressing Method Based on NAND Flash Multichannel Storage System[J]. 2018, 35(9): 32-36. DOI：

摘要

针对NAND Flash存储器的工作原理和物理特性

大容量固态存储系统可以引入多通道并行技术来支持高速数据传输.文章针对闪存阵列存储系统提出了一种新的编址方式—FVLA(Flash Virtual Layer Address)

该编址方式能很好地体现闪存系统的驱动顺序

而且具有灵活的可配置性.利用该编址方式设计出一种基于超级页的地址映射方法

通过仿真证明了该映射方式能很好地执行并行操作并大幅降低了映射表所占用的存储空间.

Abstract

In view of the working principle and physical characteristics of NAND Flash devices

mass solid state memory system can introduce multi-channel parallel technology to support high-speed data transmission.This paper proposes a new addressing method for Flash Array Storage System-FVLA (Flash Virtual Layer Address)

which can well reflect the operation sequence of flash memory system and can be configured flexibly.This paper uses the addressing mode to design an address mapping method based on superpage. The simulation results show that the mapping method can perform parallel operations and greatly reduce the memory space occupied by the mapping table.

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references

Grupp L M, Caulfield A M, Coburn J, et al. Characterizing flash memory: anomalies, observations, and applications[C]//Proceedings of the 42nd International Symposium on Microarchitecture(MICRO'09). New York, NY, 2009: 20-32.

Yan Hua, Yao Qian. An efficient file-aware garbage collection algorithm for NAND Flash-based consumer[J]. IEEE Transactions on Consumer Electronics, 2014, 60(4):623-627. DOI: 623

Agrawal N, Prabhakaran V, Wobber T, et al. Design Tradeoffs for SSD Performance[C]//Proceedings of the 2008 USENIX Annual Technical Conference(USENIX'08). San Diego, CA, 2008: 89-101.

Gupta, Kim Y, Urgaonkar B. DFTL: a flash translation layer employing demand-based selective of page-level address mapping[C]//Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systemd(ASPLOS'09). Washington, DC, 2009: 9-22.

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胡洋.高性能固态盘的多级并行性及算法研究[D].武汉: 华中科技大学, 2012.

Park C, Cheon W, Kang J, et al. A reconfigurable FTL architecture for NAND flash-based applications[J]. ACM Transactions on Embedded Computing Systems, 2008, 7(2): 60-71. DOI: 60

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