基于忆阻器的逻辑门和二位吠陀乘法器设计

刘海峰; 方芳; 王伟; 王彬

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基于忆阻器的逻辑门和二位吠陀乘法器设计

更新时间：2026-09-04

- 基于忆阻器的逻辑门和二位吠陀乘法器设计
- Design of the Logic Gate and Two-bit Vedic Multipliers Based on Memristors
- 微电子学与计算机 2018年35卷第10期页码：46-52
- 作者机构：
  
  1. 合肥工业大学计算机与信息学院,安徽,合肥,230009
  2. 合肥工业大学管理学院,安徽,合肥,230009
- 作者简介：
- 基金信息：
  
  国家自然科学基金重点项目 61432004国家自然科学基金 61474035国家自然科学基金 61204046国家自然科学基金 61306049安徽省科技攻关项目 1206c0805039安徽省自然科学基金 1508085QF129教育部新教师基金 20130111120030
- DOI：
  中图分类号：
- 纸质出版：2018
- 稿件说明：
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刘海峰, 方芳, 王伟, 王彬. 基于忆阻器的逻辑门和二位吠陀乘法器设计[J]. 微电子学与计算机, 2018, 35(10): 46-52.

LIU hai-feng, FANG Fang, WANG Wei, et al. Design of the Logic Gate and Two-bit Vedic Multipliers Based on Memristors[J]. 2018, 35(10): 46-52.
刘海峰, 方芳, 王伟, 王彬. 基于忆阻器的逻辑门和二位吠陀乘法器设计[J]. 微电子学与计算机, 2018, 35(10): 46-52. DOI：

LIU hai-feng, FANG Fang, WANG Wei, et al. Design of the Logic Gate and Two-bit Vedic Multipliers Based on Memristors[J]. 2018, 35(10): 46-52. DOI：

摘要

忆阻器是一种新型的无源元件

它拥有纳米级的尺寸、非线性以及记忆功能等特点

在模型分析、基础电路设计、电子元件设计、集成电路设计、神经突触等方面得到了运用.该文设计了一种混合CMOS忆阻器逻辑门电路

使用基于忆阻器的与门和或门、基于CMOS工艺的反相器

混合实现了基于忆阻器的异或门电路

进而组合已实现的逻辑门电路完成二位吠陀乘法器的设计.实验结果表明

设计的二位吠陀乘法器

相较于已有的二位吠陀乘法器

在完成相同功能时

功耗约为原来的80%和面积开销为原来的76%.

Abstract

Memristor is a new type of passive components

it has the characteristics of nanometer size

non-linearity and memory function.And it has been applied in model analysis

basic circuit design

electronic component design

integrated circuit design

synaptic and other aspects. In this paper

a hybrid CMOS memristor logic gate is designed

which uses an AND gate and OR gate based on memristor and an inverter based on CMOS process to realize an exclusive OR gate circuit based on memristor. Then

the two-bit Vedic multipliers are implemented using the memristor logic gate designed in this paper. The experimental results show that the two-bit Vedic multipliers designed in this paper compared with the existing two-bit Vedic multipliers

consumes approximately 80% of the original power and 76% of the area overhead when performing the same function.

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references

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