This paper proposes an imperfect loop mapping method for course-grained reconfigurable architecture. Our method iteratively adopts the loop fission

from the outermost level to innermost level

to generate perfect loops. Then the method generates virtual configuration package for each perfect loop

and the technique of configuration package combination is used. At last

the combined configuration package is mapped on the reconfigurable array. This method pays attention to both the efficiency and reconfiguration frequency of reconfigurable processor. Compared to existing dual-pipelining method

our method generates 24.2% more PE utilization rate and reduces 61.7% reconfiguration frequency.