1. 中国科学院 机构 微电子研究所,北京,100029
2. 中国科学院大学 机构,北京,100049
纸质出版:2018
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徐永志, 马骁, 张小宾, 郑占旗, 廖安谋, 赵振亚, 张立军. 30 MHz~512 MHz FSK/OOK双模射频发射机设计[J]. 微电子学与计算机, 2018, 35(11): 57-61.
XU Yong-zhi, MA Xiao, ZHANG Xiao-bin, et al. Design of 30 MHz~512 MHz FSK/OOK Dual-mode RF Transmitter[J]. 2018, 35(11): 57-61.
本文实现了一种支持FSK
OOK双模式的射频发射机芯片.该发射机芯片集成了四阶二型锁相环和开关功放
内置环路滤波器
采用了偏置拷贝环路技术降低了电荷泵参考杂散
通过调整可配置分频网络的分频比
实现了30 MHz~512 MHz频率覆盖
改变小数分频的分频比和调整具有工艺、温度补偿特性的开关功放的通断实现FSK
OOK双模发射.该芯片采用SMIC 0.18 μm 1P4M工艺
版图面积1.05 mm*1.35 mm
总体功耗为16 mW.
A CMOS transmitter supporting On-Off Keying (OOK) and Frequency Shift Keying (FSK) modulation is proposed. The transmitter integrating 4th-order TypeⅡPhase-Locked Loop
a switched-mode PA and a built-in loop filter adopts a Replica_Bias_Loop technique to reduce charge pump reference spur
and achieves a 30 MHz-512 MHz frequency coverage by adjusting the configurable network frequency division ratio. FSK/OOK modulation is implemented by changing fractional frequency division ratio and switching power amplifier with process and temperature compensation on and off. Implemented in SMIC 0.18 μm1P4M process
the transmitter occupys an area of 1.05 mm*1.35 mm and the overall power consumption is 16 mW from a 1.8 V power supply.
Brian A Floyd. A 16~18.8 GHz sub integer-N frequency synthesizer for 60GHz transceivers[J]. IEEE Journal of Solid-State Circuits, 2008, 43(5):1076-1086. DOI: 1076
Berlin Muer B D, Steyaert M. CMOS fractional-N synthesizers[M]. Berlin: Springer, 2003.
Amaral W, Castro W A, Coelhof, et al. A 2.4 GHz transceicer for wireless sensor network[C]//8th Int Caribbean Conf Dev Circ Syst. Playa del Carmen. Mexico, 2012: 1-4.
张刚.CMOS集成锁相环设计[M].北京:清华大学出版社, 2013.
Eythan Familier, Ian Galton. Second and third-order noise shaping digital quantizers for low phase noise and nonlinearity-induced spurious tones in fractional-N PLLs[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2016, 63(6):836-847. DOI: 836
Wei Lv, Lu Huang, Xuefei Bai. A 4 GHz low power glitch-free phase-switching divide-by-15/16 prescaler in 0.18 μm CMOS[C]//Ultra-Wideband (ICUWB) 2010 IEEE International Conference. Nanjing, China, 2010: 1-4.
Best R E. Phase locked loops: design simulation and applications[M].北京:清华大学出版社, 2004.
Sleiman Bou Sleiman, Jad G Atallah, Saul Rodriguez, et al. Optimal Σ△ modulatior architectures for fractional-N frequency synthesis[J]. IEEE Transactions on Very Large Scale Integration Systems, 2010, 18(2):194-200. DOI: 194
Everett G Farr. A power wave theory of antennas and coupling into complex systems[C]//General Assembly and Scientific Symposium. URSI, GASS, 2014: 1-4. DOI: 10.1109/URSIGASS.2014.6929507.
RHEE W.Design of high-performance CMOS charge pumps in phase-locked loops[J]. IEEE Int Symp Circ Syst, 1999(2):545-548. DOI: 545
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