面向可容错计算的近似Booth乘法器设计

操天; 刘伟强; 朱玉莹

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面向可容错计算的近似Booth乘法器设计

更新时间：2026-09-04

- 面向可容错计算的近似Booth乘法器设计
- Design of Approximate Booth Multipliers for Error-Tolerant Computing
- 微电子学与计算机 2018年35卷第7期页码：67-71
- 作者机构：
  
  南京航空航天大学电子信息工程学院,江苏,南京,210016
- 作者简介：
- 基金信息：
  
  国家自然科学基金青年科学基金 61401197南京航空航天大学研究生创新基地(实验室)开放基金 kfjj20160410
- DOI：
  中图分类号：
- 纸质出版：2018
- 稿件说明：
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操天, 刘伟强, 朱玉莹. 面向可容错计算的近似Booth乘法器设计[J]. 微电子学与计算机, 2018, 35(7): 67-71.

CAO Tian, LIU Wei-qiang, ZHU Yu-ying. Design of Approximate Booth Multipliers for Error-Tolerant Computing[J]. 2018, 35(7): 67-71.
操天, 刘伟强, 朱玉莹. 面向可容错计算的近似Booth乘法器设计[J]. 微电子学与计算机, 2018, 35(7): 67-71. DOI：

CAO Tian, LIU Wei-qiang, ZHU Yu-ying. Design of Approximate Booth Multipliers for Error-Tolerant Computing[J]. 2018, 35(7): 67-71. DOI：

摘要

本文提出了一种通过近似因子来实现精度可调的近似Booth乘法器的设计方法

并利用归一化的平均误差距离及功耗延时的乘积来评估近似乘法器的可靠性与硬件复杂度.综合考虑可靠性与硬件复杂度

本文所设计的近似乘法器与已有设计方案相比性能更优

并在图像处理等可容错计算应用中显示出较好的应用价值.

Abstract

This paper proposes the approximate Booth multipliers whose accuracy can be adjusted by changing the so called approximate factor. The reliability and hardware complexity of the proposed multiplier are evaluated by the normalized mean error distance (NMED) and power-delay product (PDP). Considering both the reliability and hardware complexity

the proposed designs are better than the existing approximate Booth multipliers. Case studies into image processing show the validity of the proposed approximate multipliers.

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references

Cho K, Lee K, Chung J. Design of low-error fixed-width modified booth multiplier[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, 12(5): 522-531. DOI: 522

Jiang H, Han J, Qiao F. Approximate radix-8 booth multipliers for low-power and high-performance operation[J]. IEEE Transactions on Computers, 2016, 65 (8) :2638-2644. DOI: 2638

Momeni A, Han J, Montuschi P, et al. Design and analysis of approximate compressors for multiplication[J]. IEEE Transactions on Computers, 2015, 64(4): 984-994. DOI: 984

Liu W, Qian L, Wang C, et al. Design of approximate radix-4 booth multipliers for error-tolerant computing[J]. IEEE Transactions on Computers, 2017, 66(8): 1435-1441. DOI: 1435

Chang C, Gu J, Zhang M. Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2004, 51(10): 1985-1997. DOI: 1985

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Wang Z, Bovik A, Sheikh H et al. Image quality assessment: From error visibility to structural similarity[J]. IEEE Transactions on Image Processing, 2004, 13(4):600-612. DOI: 600

崔晓平, 高鹏辉, 尹洁珺, 等. 54位高速冗余二进制乘法器的设计[J].微电子学与计算机, 2014, 31(4):140-143. DOI: 140

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