In this paper

an AHB Matrix bus system which is compatible with AMBA master and slave devices is designed

aiming at realizing multiple master devices to access multiple slave devices in parallel. This bus system can effectively improve the bandwidth and reduce the delay caused by multiple master accessing the slave. Its main structure and micro-architecture is elaborated with the design ideas of each module. The bus system is implemented with Verilog HDL in RTL behavior level. Slave address and master/slave number supported can be configurable via parameterized design. Finally

the verification environment is set up to test the basic functions of the bus matrix. It is proved that in the testcase of the 8 masters inputs

Compared with the traditional AHB bus

the AHB bus matrix under the condition of multiple masters cross-access multiple slaves can reduce the bus access delays up to 3 times and increase the bus throughput by 8.5 times.