基于拥塞和热点感知的低延时片上网络路由器设计

刘炎华; 石世领; 孙海燕; 孙玲; 黄新明

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基于拥塞和热点感知的低延时片上网络路由器设计

更新时间：2026-09-04

- 基于拥塞和热点感知的低延时片上网络路由器设计
- Congestion and Hotspot Aware Router Design for Low Latency Network-on-Chip
- 微电子学与计算机 2018年35卷第6期页码：122-127
- 作者机构：
  
  1. 南通大学机构电子信息学院,江苏,南通,226019
  2. 伍斯特理工学院电气工程与计算机系,伍斯特,01609
- 作者简介：
- 基金信息：
  
  国家自然科学基金面上项目 61571246江苏省高校自然科学研究重大项目 16KJA510006江苏省科技厅重点研发计划项目 BE2016007-2南通市科技应用基础研究计划项目 GY12015004
- DOI：
  中图分类号：
- 纸质出版：2018
- 稿件说明：
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刘炎华, 石世领, 孙海燕, 孙玲, 黄新明. 基于拥塞和热点感知的低延时片上网络路由器设计[J]. 微电子学与计算机, 2018, 35(6): 122-127.

LIU Yan-hua, SHI Shi-ling, SUN Hai-yan, et al. Congestion and Hotspot Aware Router Design for Low Latency Network-on-Chip[J]. 2018, 35(6): 122-127.
刘炎华, 石世领, 孙海燕, 孙玲, 黄新明. 基于拥塞和热点感知的低延时片上网络路由器设计[J]. 微电子学与计算机, 2018, 35(6): 122-127. DOI：

LIU Yan-hua, SHI Shi-ling, SUN Hai-yan, et al. Congestion and Hotspot Aware Router Design for Low Latency Network-on-Chip[J]. 2018, 35(6): 122-127. DOI：

摘要

为了改善片上网络路由器的通信延时

提高路由器的可靠性

通过改良路由器架构、优化路由器关键路径

结合设计的基于拥塞和热点感知路由算法

提出了一种低延时片上网络路由器设计方法.相同配置下的综合结果表明本文设计的路由器与CONNECT路由器相比具有工作速度快、传输延时低的优点; Hotspot负载模型下的测试结果显示该路由算法明显优于传统的超前XY路由算法.

Abstract

To decrease the communication latency and improve the reliability of the routers in the Network-on-Chip

a low latency router based on congestion- and hotspot-aware routing algorithm is proposed by building a novel virtual channel router architecture and optimizing its critical path. The experimental results show that the proposed router can achieve faster operating frequency and lower transmission latency when compared with CONNECT router. Under Hotspot traffic

our routing algorithm is obviously superior to the look-ahead XY routing.

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references

Becker D U. Efficient microarchitecture for network-on-chip routers[D]. California: Stanford University, 2012.

Ye L, McCanny J, Sezer S. Exploring Virtual-Channel Architecture in FPGA based Networks-on-Chip[C] //Proceedings of the 24th IEEE International System on Chip Conference. Los Alamitos: IEEE Computer Society Press, 2011: 302-307.

Dimitrakopoulos G, Chrysos N, Galanopoulos K. Fast arbiters for on-chip network switches[C] //Proceedings of the 26th IEEE International Conference on Computer Design. Los Alamitos: IEEE Computer Society Press, 2008: 664-670.

Papamichael M K, Hoe J C. The CONNECT Network-on-Chip Generator[J]. Computer, 2015, 48(12): 72-79. DOI: 72

Mullins R, West A and Moore S. The Design and Implement of a Low Latency On Chip Network[C] //Proceedings of the Asia and South Pacific Design Automation Conference. Los Alamitos: IEEE Computer Society Press, 2006: 164-169.

Krishna T, Kumar A, et al. NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication[C] //Proceedings of the 16th Annual Symposium on High-Performance Interconnects. Los Alamitos: IEEE Computer Society Press, 2008: 11-20.

Ye L, McCanny J, Sezer S. Generic Low-Latency NoC Router Architecture for FPGA Computing Systems[C] //Proceedings of the 21st International Conference on Filed Programmable Logic and Applications. Los Alamitos: IEEE Computer Society Press, 2011: 82-89.

张庆利, 刘成, 肖立伊, 等.支持确定性/自适应性路由的低延时片上路由器设计[J].计算机辅助设计与图形学学报, 2009, 21(12): 1706-1714. DOI: 1706

Kreider M, Bar R, Beck D, et al. Open borders for sys-tem-on-a-chip buses: A wire format for connecting large physics controls[J]. Physical Review Special Topics-accelerators and Beams, 2012, 15(8):1-10. DOI: 1

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