合肥工业大学 电子科学与应用物理学院,安徽,合肥,230009
纸质出版:2018
移动端阅览
张章, 徐姚华, 解光军. 一种基于LMS算法的流水线ADC数字校准算法[J]. 微电子学与计算机, 2018, 35(9): 103-107.
ZHANG Zhang, XU Yao-hua, XIE Guang-jun. A Digital Calibration Algorithm for Pipeline ADC Based on LMS Algorithm[J]. 2018, 35(9): 103-107.
文章提出了一种基于LMS算法
自动迭代一阶三阶误差系数的后台数字校准技术.该校准技术能够有效地减小电容失配、运放有限增益等非线性因素对系统的影响
提高系统的线性度.使用Simulink对所搭建的16位流水线ADC进行仿真
当采样频率为100 MHz
输入信号频率为45 MHz时
通过校准
流水线ADC的有效位数ENOB从9.6位提升至15.7位
信噪比SNR由67.5 dB提升至97.6 dB
无杂散动态范围SFDR由64.9 dB提升至110.8 dB.
This paper presents a back-end digital calibration technology
which is based on LMS algorithm and can iterates first- and third-order error coefficients automatically. The calibration technology can reduce the influence of capacitive mismatch
op amp limited gain and other nonlinear factors
and improve linearity of the system effectively. The entire digital calibration system was modeled with Simulink. The simulation results showed that the ENOB
SNR
and SFDR of the pipeline ADC with sampling rate of 100 MHz and input rate of 45 MHz were improved from 9.6 bit to 15.7 bit
67.5 dB to 97.6 dB and 64.9 dB to 110.8 dB respectively after calibration.
Miyahara Y, Sano M, Koyama K, et al. A 14b 60 MS/s Pipelined ADC Adaptively CancellingOpamp Gain and Nonlinearity[J]. IEEE Journal of Solid-State Circuits, 2014, 49(2):416-425. DOI: 416
Lewis S H, Gray P R. A pipelined 5-Msample/s 9-bit analog-to-digital converter[J]. Solid-State Circuits, IEEE Journal of, 1987, 22(6):954-961. DOI: 954
Ryu S T, Ray S, Song B S, et al. A 14-b linear capacitor self-trimming pipelined ADC[J]. IEEE Journal of Solid-State Circuits, 2004, 39(11):2046-2051. DOI: 2046
Zhang S, Ding L, Xu J, et al. Digital Background Calibration of MDAC Stage Gain Error and DAC Error in Pipelined ADC[C]// 2010 10thieee international conference on solid-state and integrated circuit technology. 2010: 251-253.
Abou-El-Kheir N T, Khedr M E, Abbas M. A fast power efficient equalization-based digital background calibration technique for pipelined ADC[C]// Mixed Design of Integrated Circuits % Systems. IEEE, 2014: 108-112.
Chen H, Deng H, Yin Y. A correlation-based background calibration technology for the pipeline A/D Converter[C]// IEEE International Conference on Solid-State and Integrated Circuit Technology. IEEE, 2017.
Ray S, Song B S. A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured Capacitor Matching[J]. IEEE Journal of Solid-State Circuits, 2007, 42(3):463-474. DOI: 463
熊召新, 蔡敏, 贺小勇.基于比较器抖动的数字后台校准算法[J].华中科技大学学报(自然科学版), 2013, 41(8):24-29. DOI: 24
戴澜, 周玉梅, 胡晓宇, 等.一种流水线ADC数字校准算法实现[J].半导体学报, 2008, 29(5):993-997. DOI: 993
Zhou Liren, Luo Lei, Ye Fan, 等. A 12-bit 100 MS/s pipelined ADC with digital background calibration采用后台数字校准的12位100MHz流水线模数转换器[J]. Journal of Semiconductors, 2009, 30(11):109-113. DOI: 109
赵郁炜.一种应用于流水线ADC的自适应后台校正技术[J].微电子学, 2014, 44(3):281-284. DOI: 281
Panigada A, Galton I. Digital Background Correction of Harmonic Distortion in Pipelined ADCs[J]. IEEE Transactions on Circuits % Systems I Regular Papers, 2006, 53(9):1885-1895. DOI: 1885
0
浏览量
58
下载量
0
CSCD
关联资源
相关文章
相关作者
相关机构
京公网安备11010602201714号