In this paper

the programmable delay element of the input and output track module of the FPGA chip is studied. By designing the programmable delay element with wide delay adjustment range

high delay adjustment precision and many delay series

the requirements of the delay adjustment of bus signals to align bus edges or meet the requirement of setup/hold time are satisfied. The designmethod is proposed in detail. In the design

the fine-grained delay element and coarse-grained delay element are used to increase the step precision and delay range. Finally

the delay element with the precision of 100ps and the range of 4.58ns is implemented under the condition of fewer control vector

lower power dissipation and smaller area. The simulation result indicate that the power and area are only 34.5% and 55.9% compared with the traditional inverter chain structure.