3 200 Mbps DDR4 PHY的物理设计优化

任小敏; 苏皆磊; 倪哲勤; 王琴

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3 200 Mbps DDR4 PHY的物理设计优化

更新时间：2026-09-04

- 3 200 Mbps DDR4 PHY的物理设计优化
- Optimization in physical design of 3 200 Mbps DDR4 PHY
- 微电子学与计算机 2019年36卷第7期页码：1-5
- 作者机构：
  
  1. 上海交通大学电子信息与电气工程学院,上海,200240
  2. 世芯电子有限公司,上海,200030
- 作者简介：
- 基金信息：
  
  自然基金号 61176037
- DOI：
  中图分类号：
- 纸质出版：2019
- 稿件说明：
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任小敏, 苏皆磊, 倪哲勤, 王琴. 3 200 Mbps DDR4 PHY的物理设计优化[J]. 微电子学与计算机, 2019, 36(7): 1-5.

REN Xiao-min, SU Jie-lei, NI Zhe-qin, et al. Optimization in physical design of 3 200 Mbps DDR4 PHY[J]. 2019, 36(7): 1-5.
任小敏, 苏皆磊, 倪哲勤, 王琴. 3 200 Mbps DDR4 PHY的物理设计优化[J]. 微电子学与计算机, 2019, 36(7): 1-5. DOI：

REN Xiao-min, SU Jie-lei, NI Zhe-qin, et al. Optimization in physical design of 3 200 Mbps DDR4 PHY[J]. 2019, 36(7): 1-5. DOI：

摘要

以一款基于TSMC 16 nm FinFET工艺的HPC(High Performance Computing)芯片中DDR4 PHY模块为研究对象

提出了其物理设计及优化方案

完成了DDR4 PHY的布图规划和布局、时钟树综合与优化和时序收敛分析.布图规划时考虑到宏单元和IO单元的特性再结合面积和时序等性能的优化确定了DDR4 PHY的布局形状.时钟树综合时

对比分析了传统的时钟树综合CTS和优化设计过的多源时钟树综合MSCTS

设计了针对DDR4 PHY模块特点的大型多位缓冲器M2M8

其驱动距离可以达到1200 μm.仿真实验结果表明

优化后的时钟树结构级数从65级降到19级

时钟最大延迟最多降低了48.37%

时钟偏差减少了52.33%

功耗降低了17.24%

DDR4 PHY的各项性能优化结果显著

达到实验目的.

Abstract

The physical design and its optimization were proposed for the DDR4 PHY of one High Performance Computing chip based on TSMC 16 nm FinFET process technology

including the floorplan、placement、clock tree synthesis and its optimization and timing closure analysis. Take macros and IO cells combined with area and timing optimization into account to fix the floorplan shape of DDR4 PHY. Compare the typical CTS with optimized MSCTS and analyze their differences when clock tree synthesis. Design multi-bit buffer M2M8 for DDR4 PHY whose drive distance can be 1200 μm. Simulation results show that optimized clock tree structure level decreases from 65 to 19

max clock latency decreases by 48.37%

clock skew decreases by 52.33%

power decreases by 17.24%

the performance optimization results are prominent and achieve the goal of experiment.

关键词

Keywords

references

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