基于Bus-Invert编码的低功耗AES加密电路设计

李凯利; 张卫航; 郭桂良

Chinese

您当前的位置：

首页 >

文章列表页 >

基于Bus-Invert编码的低功耗AES加密电路设计

更新时间：2026-09-04

- 基于Bus-Invert编码的低功耗AES加密电路设计
- Design of low power AES encryption circuit based on Bus-Invert coding
- 微电子学与计算机 2019年36卷第7期页码：27-31
- 作者机构：
  
  1. 中国科学院大学机构微电子学院,北京,100049
  2. 中芯国际集成电路制造有限公司,上海,201210
- 作者简介：
- 基金信息：
- DOI：
  中图分类号：
- 纸质出版：2019
- 稿件说明：
移动端阅览
李凯利, 张卫航, 郭桂良. 基于Bus-Invert编码的低功耗AES加密电路设计[J]. 微电子学与计算机, 2019, 36(7): 27-31.

LI Kai-li, ZHANG Wei-hang, GUO Gui-liang. Design of low power AES encryption circuit based on Bus-Invert coding[J]. 2019, 36(7): 27-31.
李凯利, 张卫航, 郭桂良. 基于Bus-Invert编码的低功耗AES加密电路设计[J]. 微电子学与计算机, 2019, 36(7): 27-31. DOI：

LI Kai-li, ZHANG Wei-hang, GUO Gui-liang. Design of low power AES encryption circuit based on Bus-Invert coding[J]. 2019, 36(7): 27-31. DOI：

摘要

随着无线设备的广泛应用

半导体应用市场对低功耗加密电路提出了更高的要求.降低功耗可以延长无线设备的工作时间以及待机时间

而加密电路能够保障数据传输的安全性.在低功耗设计方法中

通过对信号编码来降低信号翻转率具有重要的研究意义.BI(Bus-Invert)编码技术可以降低随机信号的翻转率

在AES加密电路中引入BI编码技术

对电路输入数据BI编码

可得到一种改进型的低功耗AES加密电路.经验证

与原电路相比

改进型电路的ShiftRow、MixColumn、SubByte、KeyExpansion各子模块每周期内的平均翻转率分别降低了68%、42%、50%、46%

动态功耗降低了36.4%.

Abstract

With the widespread use of wireless devices

the semiconductor application market has placed higher demands on low-power encryption circuits. Reducing power consumption can extend the operating time and standby time of wireless devices

while encryption circuits ensure data transmission security. In the low-power design method

it is of great research significance to reduce the signal toggle rate by coding the signal. BI (Bus-Invert) coding technology can reduce the toggle rate of random signals. By introducing BI coding technology in AES encryption circuit and encoding input data

an improved low-power AES encryption circuit can be obtained. It is verified that compared with the original circuit

the average toggle rate of the ShiftRow

MixColumn

SubByte

and KeyExpansion sub-modules of the improved circuit is reduced by 68%

42%

50%

and 46%

respectively

and the dynamic power consumption is reduced 36.4%.

关键词

Keywords

references

ZHANG J Y, ZUO Q H, ZHANG T B. Reducing the power consumption of the AES S-Box by SSC[C]// International Conference on Wireless Communications, Networking and Mobile Computing. Shanghai: IEEE, 2007: 2226-2229.

CHOI H S, CHOI J H, KIM J T. Low-Power AES design using parallel architecture[C]// 2008 International Conference on Convergence % Hybrid Information Technology. Daejeon: IEEE, 2008: 413-416.

NIST. FIPS PUBS 197. Advanced Encryption Standard (AES)[S].America: National Institute of Standards and Technology, 2001.

FLETCHER R J. Integrated circuit having outputs configured forreducedstate changes: U.S. Patent 4667337[P].1987-5-19.

HAGHIGHIZADEH F, ATTARZADEH H, SHARIFKHANI M. A compact 8-Bit AES crypto-processor[C]// 2010 Second International Conference on Computer % Network Technology. Bangkok: IEEE, 2010: 71-75.

GOLSON S. One-hot state machine design for FPGAs[C]// Proc. 3rdAnnual PLD Design Conference % Exhibit, 1993: 1.1.3.B.

HESHAM S, ABD EL GHANY M A, HOFMANN K. High throughput architecture for the advanced encryption standard algorithm[C]// 17th International Symposium on Design % Diagnostics of Electronic Circuits % Systems. Warsaw: IEEE, 2014: 167-170.

BUI D H, PUSCHINI D, BACLES-MIN S, et al. Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications[C]// 2016 International Conference on IC Design and Technology (ICICDT). Ho Chi Minh City: IEEE, 2016: 1-4.

MEHTA H, OWENS R M, IRWIN M J. Some issues in gray code addressing[C]// Proceedings of the Sixth Great Lakes Symposium on VLSI. Ames: IEEE, 1996: 178-181.

BERTONI G, MACCHETTI M, NEGRI L, et al. Power-efficient ASIC synthesis of cryptographic sboxes[C]// Acm Great Lakes Symposium on VLSI. Boston: ACM, 2004: 277-281.

浏览量

下载量

CSCD

文章被引用时，请邮件提醒。

提交

工具集

关联资源

大模型发展综述：从BERT到Deepseek的技术演进

基于区块链的AI生成内容溯源框架设计研究

基于多尺度融合与小目标增强的航拍车辆检测算法

基于反向体偏置的高增益稳定性高温运放设计

面向处理器分支预测单元的Spectre攻击轻量化防御方法