一种基于忆阻器的可扩展乘法器设计

郑子遇; 江先阳; 汤知日

Chinese

您当前的位置：

首页 >

文章列表页 >

一种基于忆阻器的可扩展乘法器设计

更新时间：2026-09-04

- 一种基于忆阻器的可扩展乘法器设计
- An expandable multiplier design based on memristor
- 微电子学与计算机 2019年36卷第11期页码：60-64
- 作者机构：
  
  武汉大学物理科学与技术学院物理国家级实验教学示范中心,湖北,武汉,430072
- 作者简介：
- 基金信息：
  
  国家自然科学基金 61072135中央高校基本科研业务费专项资金 2042017gf0075湖北省自然科学基金 2017CFB721
- DOI：
  中图分类号：
- 纸质出版：2019
- 稿件说明：
移动端阅览
郑子遇, 江先阳, 汤知日. 一种基于忆阻器的可扩展乘法器设计[J]. 微电子学与计算机, 2019, 36(11): 60-64, 69.

ZHENG Zi-yu, JIANG Xian-yang, TANG Zhi-ri. An expandable multiplier design based on memristor[J]. 2019, 36(11): 60-64.
郑子遇, 江先阳, 汤知日. 一种基于忆阻器的可扩展乘法器设计[J]. 微电子学与计算机, 2019, 36(11): 60-64, 69. DOI：

ZHENG Zi-yu, JIANG Xian-yang, TANG Zhi-ri. An expandable multiplier design based on memristor[J]. 2019, 36(11): 60-64. DOI：

摘要

针对在基于忆阻器的全加器设计中

在级联时前级结构需要向后级结构输出的结果以阻值的形式储存在忆阻器中无法直接获取的问题

设计了一种将忆阻器的阻值转换为电压值以方便输出的新结构.基于提出的新结构

改进了基于忆阻器的全加器设计

以此为基础设计了基于忆阻器的乘法器

并实现了乘法器的位宽扩展.以两位乘法器为例

基于HP模型

利用LTspice XVII仿真

展示提出的读出结构可以有效支持乘法器的位宽扩展.

Abstract

For memristor-based full adder

the output result of pre-structure is necessary to be transferred to the post-structure

which is stored in the form of resistance value and cannot be utilized directly by the post-structure. Targeting at this problem

a novel read-out structure is proposed which converts the value of memristor resistance into voltage value. Based on the proposed structure

a memristor based full adder has been improved and based on this memristor based multiplier is designed and bit-width can be freely expanded. By two-bit multiplier example

based on HP memristor model and by LTspice simulation

it is demonstrated that the proposed structure can efficiently support bit-width expandation of memristor based multiplier.

关键词

Keywords

references

STRUKOV D B, SNIDER G S, STEWART D R, et al. The missing memristor found[J]. Nature, 2008, 453(7191):80-83. DOI: 80

North-Holland CHO K R, LEE S J, ESHRAGHIAN K. Memristor-CMOS logic and digital computational components[M]. North-Holland:Elsevier Science Publishers B. V. 2015.

AHMAD K, ABDALHOSSEIN R. Novel design for a memristor-based full adder using a new IMPLY logic approach[J]. Journal of Computational Electronics, 2018, 17(3): 1303-1314. DOI: 1303

XIE L, NGUYEN H A D, TAOUIL M, et al. Fast boolean logic mapped on memristor crossbar[C]// IEEE International Conference on Computer Design. New York City, USA, IEEE Computer Society, 2015.

邓辉.基于忆阻器的加法器设计及其仿真分析[D].武汉: 华中科技大学, 2016.

BORGHETTI J, SNIDER G S, KUEKES P J, et al. 'Memristive's witchese nable'stateful'logic operations via material implication[J]. Nature, 2010, 464(7290):873-876. DOI: 873

CHUA L. Memristor-The missing circuit element[J]. IEEE Transactions on Circuit Theory, 1971, 18(5):507-519. DOI: 507

ZHANG Y, SHEN Y, WANG X, et al. A novel design for memristor-based logic switch and crossbar circuits[J]. IEEE Transactions on Circuits and Systems Ⅰ: Regular Papers, 2015, 62(5):1402-1411. DOI: 1402

WANG X, CHEN Q, WAN H, et al. A logic circuit design for perfecting memristor-based material implication[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36(2):279-284. DOI: 279

PAPANDROULIDAKISG, VOURKAS I, VASILEIADIS N, et al. Boolean logic operations and computing circuits based on memristors[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2014, 61(12):972-976. DOI: 972

ZHU X, YANG X, WU C, et al. Performing stateful logic on memristor memory[J]. IEEE Transactions on Circuits % Systems Ⅱ Analog % Digital Signal Processing, 2013, 60(10):682-686. DOI: 682

ZHANG Y, SHEN Y, WANG X, et al. A novel design for a memristor-based or gate[J]. IEEE Transactions on Circuits % Systems Ⅱ Express Briefs, 2015, 62(8):781-785. DOI: 781

浏览量

下载量

CSCD

文章被引用时，请邮件提醒。

提交

工具集

关联资源

基于忆阻的新型二象限模拟乘法器

一种基于双忆阻的SOFM神经网络系统设计研究

基于忆阻器的模拟人工神经元电路设计

基于忆阻器的正弦波振荡电路设计

一种改进的忆阻器的SPICE模型及其仿真