IEEE. IEEE 1005 standard definitions and characterization of floating gate semiconductor arrays[C]// IEEE Standards Department, Piscataway, 1999.

潘中良, 系统芯片SOC的设计与测试[M].北京: 科学出版社, 2009: 250-251.

MOHAMMAD M, SALUJA K, YAP A. Testing flash memories[C]//13th international Conference on VLSI Design. Calcutta, India, 2000: 406-411.

MOHAMMAD G MOHAMMAD, KEWAL K SALUJA. Flash memory disturbances: modeling and test[C]//Proceedings 19th IEEE VLSI Test Symposium. VTS 2001. Marina Del Rey, CA, USA, 2001.

LARCHER L, PAVAN P, MAURELLI A. Flash memories for SOC: An overview on system constraints and technology[C]//Proc.IEEE Int.Workshop System-on-Chip Real-Time Appl., Banff, AB, Canada, 2005: 73-77.

LAWTON G. Improved flash memory grows in popularity[J]. Computer, 2006, 39(1):16-18. DOI: 16

PIERPAOLO NICOSIA, FULVIO NAVA. Test strategies on non volatile memories electrical wafer sort on NAND, nor flash and phase change memories[C]// 22nd IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, CA, USA, 2007: 11-18.

Chichester, UK VAN DE GOOR A J. Testing semiconductor memories: theory and practice[M]. Chichester, UK: John Wiley % Sons, Inc, 1991.

鉴海防, 王占和, 李印增, 等. SoC嵌入式Flash存储器的内建自测试设计[J].微电子与计算机, 2005, 22(4):87-91. DOI: 87

JEN-CHIEH YEH, KUO-LIANG CHENG, YUNG-FA CHOU, et al. Flash memory built-in self-test using March-like algorithms[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007(26): 1101-1113. DOI: 1101