1. 中国科学院大学,北京,100190
2. 中国科学院 电子学研究所,北京,100190
纸质出版:2019
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赵思琦, 高同强, 卢新, 张恒, 赵湛, 杨海钢. 一种用于FBAR环境信号检测芯片的全集成低压差线性稳压器电路[J]. 微电子学与计算机, 2019, 36(10): 73-77, 82.
ZHAO Si-qi, GAO Tong-qiang, LU Xin, et al. A high performance capacitorless low-dropout regulator for the FBAR sensor circuits[J]. 2019, 36(10): 73-77.
本文采用自适应功率管技术实现了一款较高性能的片上低压差线性稳压器(LDO)
其中误差放大器在增加动态偏置结构的同时引入瞬态加强级
使得全集成LDO在负载跳变时具有快速瞬态响应
稳定了输出电压.该LDO基于0.18 μm标准CMOS工艺进行设计
仿真结果表明
在电源电压3 V
输出电压1.2 V
负载电容为100pF的条件下
该LDO可稳定输出0~100 mA负载电流
实现全负载稳定.并且负载电流在200 ns内从0~100 mA跳变时
瞬态输出电压变化峰值在150 mV以内.
This paper uses adaptive power transistor technology to implement a higher performance on-chip low-dropout linear regulator (LDO)
in which the error amplifier adds a dynamic bias structure while introducing a transient boost stage
making the integrated LDO has a fast transient response during load transitions that stabilizes the output voltage. The LDO is designed based on the 0.18um standard CMOS process. The simulation results show that the LDO can stably output 0~100 mA load current under the condition of 3 V power supply voltage
1.2 V output voltage and 100 pF load capacitance
achieving full load stability. And when the load current jumps from 0 to 100 mA within 200 ns
the peak value of the transient output voltage changes to within 150 mV.
CHEAH M, MANDAL D, BAKKALOGLU B, et al. A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression[J]. IEEE Transactions on Very Large Scale Integration Systems, 2017, 25(2):1-9. DOI: 1
张萌颖.基于氧化锌薄膜体声波谐振器的传感器及系统研究[D].北京: 中国科学院大学, 2017.
LIU X, WANG S, GUO S, et al. Design of off-chip capacitor-free CMOS low-dropout voltage regulator[C]. IEEE Asia Pacific Conference on Circuits % Systems. IEEE, 2008.
LAU S K. A Low-Dropout Regulator for SoC With -Reduction[J].IEEE Journal of Solid-State Circuits, 2007, 42(3):658-664. DOI: 658
MILLIKEN R J, SILVAMART J, SANCHEZINENCIO E, et al. Full On-Chip CMOS Low-Dropout Voltage Regulator[J]. IEEE Transactions on Circuits % Systems I Regular Papers, 2007, 54(9):1879-1890. DOI: 1879
ZHAN W. An output-capacitor-free adaptively biased low-dropout regulator with sub-threshold undershoot-reduction for SoC[J]. IEEE Transactions on Circuits % Systems I Regular Papers, 2012, 59(5):1119-1131. DOI: 1119
CHONG S S, CHAN P K. A 0.9uA Quiescent Current Output-Capacitorless LDO Regulator With Adaptive Power Transistors in 65-nm CMOS[J]. IEEE Transactions on Circuits % Systems I Regular Papers, 2013, 60(4):1072-1081. DOI: 1072
QU X, ZHOU Z K, ZHANG B, et al. An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push-Pull Output Stage[J]. IEEE Transactions on Circuits % Systems II Express Briefs, 2013, 60(2):96-100. DOI: 96
李雅淑, 高超嵩, 孙向明, 等.基于0.13μm SOI CMOS工艺的高性能LDO设计[J].电子设计工程, 2018, 26(19):165-170. DOI: 165
ZHAN C, KI W H. Output-Capacitor-Free Adaptively Biased Low-Dropout Regulators[J]. IEEE Transactions on Circuits % Systems I Regular Papers, 2010, 57(5):1017-1028. DOI: 1017
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