To solve the problem of difficult test scheduling and low parallel test efficiency in three Dimensional Network-on-Chip(3D NoC)

an Hierarchical Colored Timed Petri net(HCTPN) combined with improved firefly algorithm(IFA) is proposed. The system scheduling processes and testing details are hierarchically described by HCTPN model

and the test scheduling scheme is associated with the transition sequence. In order to optimize the routing calculations

an improved routing algorithm is designed for the 3D Torus topology. On this basis

the transition sequence is mapped to a firefly individual

and the IFA combined with reverse learning mechanism and differential evolution algorithm is used to find the optimal sequence. Simulation results show that the HCTPN model can clearly characterize the scheduling process

resource constraints

and priorities of the test. And the improved routing algorithm can effectively reduce routing time

meanwhile IFA can efficiently obtain the optimal solution of test scheduling. The test time was reduced by 18.9% to the greatest extent

which effectively improved the test efficiency.