一种无线便携心电监测系统的双斜坡ADC的设计

谢向阳; 陈铭易; 王国兴

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一种无线便携心电监测系统的双斜坡ADC的设计

更新时间：2026-09-04

- 一种无线便携心电监测系统的双斜坡ADC的设计
- Design of a dual Slope ADC for wireless monitoring of electrocardiography
- 微电子学与计算机 2020年37卷第4期页码：1-6
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
  
  国家重点研发计划项目 2016YFE0116900
- DOI：
  中图分类号：
- 纸质出版：2020
- 稿件说明：
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谢向阳, 陈铭易, 王国兴. 一种无线便携心电监测系统的双斜坡ADC的设计[J]. 微电子学与计算机, 2020, 37(4): 1-6.

XIE Xiang-yang, CHEN Ming-yi, WANG Guo-xing. Design of a dual Slope ADC for wireless monitoring of electrocardiography[J]. 2020, 37(4): 1-6.
谢向阳, 陈铭易, 王国兴. 一种无线便携心电监测系统的双斜坡ADC的设计[J]. 微电子学与计算机, 2020, 37(4): 1-6. DOI：

XIE Xiang-yang, CHEN Ming-yi, WANG Guo-xing. Design of a dual Slope ADC for wireless monitoring of electrocardiography[J]. 2020, 37(4): 1-6. DOI：

摘要

本文提出了一种可以应用于低频低幅值生物电信号采集的片上集成的全差分双斜坡积分ADC，使用两个反积分参考电压扩大测量范围.为了降低失调影响使用了输入失调存储的自动调零技术，从降低功耗角度，使用了动态比较器，并通过控制动态比较器的工作时钟，让其具有休眠模式和较短时间的工作模式，更大程度地降低功耗.本文的12 bit积分型ADC由0.35 m工艺设计实现，在2 V供电、6 MHz时钟下，采样率为689.3 S/s，功耗为12 W，使用Cadence Virtuoso仿真得到其有效位数为11.8 bit.

Abstract

This paper presentsa fully on-chip fully-differential dual-slope ADC that can be used for low frequency bioelectrical signal processing

it uses two anti-integrating reference voltage for wide range input.The auto-zero technique is applied to reduce the offset of op-amp. Dynamic comparator and well-designed clock timing controller of the comparator are used to save more power. The timing controller is set to let the comparator have sleeping mode and working mode. The proposed 12 bit dual-slope ADC is implemented in 0.35 m CMOS process

the ADC has sampling rate of 689 S/s under 6MHz clock

working at 2 V supply voltage

the ADC consumes 6 A current. Simulation result shows that the effective number of bits (ENOB) for the ADC is 11.8 bit.

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references

SHETTY D, RENUKASWAMY P T. A 11-Bit Integrating Analog to Digital Converter[C]. 2016 Austrochip Workshop on Microelectronics (Austrochip), Villach, 2016: 19-23.

程天元, 吴春东, 王国兴.一种全集成交替型双积分ADC的设计[J].微电子学与计算机, 2018, 35(10):62-66. DOI: 62

DEEPU C J, XU X Y, WONG D L T, et al.A 2.3 μW ECG-On-Chip for Wireless Wearable Sensors[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2018. 65(10): 1385-1389. DOI: 1385

HONG H, LIN L, LIU C. Design of an on-scribe-line 12-bit dual-slope ADC for wafer acceptance test[C].2017 International Conference on Applied System Innovation (ICASI), Sapporo, 2017: 1751-1754.

FANG X, SRINIVASAN V, WILLS J, et al. CMOS 12 bits 50kS/s micropower SAR and dual-slope hybrid ADC[C]. 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, 2009: 180-183.

JAFARI H, SOLEYMANI L, GENOV R. 16-Channel CMOS Impedance Spectroscopy DNA Analyzer with Dual-Slope Multiplying ADCs[J]. IEEE transactions on biomedical circuits and systems, 2012, 6(5): 468-478. DOI: 468

BAKER R J.CMOSCircuit Design, Layout, and Simulation[M]. Wiley-IEEE Press, 2011.

LEVINE P M, GONG P, LEVICKY R, et al. Active CMOS sensor array for electrochemical biomolecular detection[J]. IEEE Journal of Solid-State Circuits, 2008, 43(8):1859-1871. DOI: 1859

SHAN H, RAUSCH S, JOU A, et al.A low power programmable dual-slope ADC for single-chip RFID sensor nodes[C]. 2017 IEEE 17th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Phoenix, AZ, 2017: 118-120.

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