一种提前终止单元划分的帧内预测动态可重构实现

贺飞龙; 蒋林; 刘新闯; 山蕊; 王昱; 吴皓月

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一种提前终止单元划分的帧内预测动态可重构实现

更新时间：2026-09-04

- 一种提前终止单元划分的帧内预测动态可重构实现
- An intra-prediction dynamic reconfigurable implementation of early termination unit partitioning
- 微电子学与计算机 2020年37卷第2期页码：15-19
- 作者机构：
  
  1. 西安邮电大学计算机学院,陕西,西安,710121
  2. 西安科技大学机构集成电路实验室,陕西,西安,710054
  3. 西安邮电大学机构电子工程学院,陕西,西安,710121
- 作者简介：
- 基金信息：
  
  国家自然科学基金资助项目 61834005国家自然科学基金资助项目 61772417国家自然科学基金资助项目 61802304国家自然科学基金资助项目 61602377国家自然科学基金资助项目 61874087国家自然科学基金资助项目 61634004陕西省科技统筹创新工程项目 2016KTZDGY02-04-02陕西省重点研发计划 2017GY-060陕西国际科技合作计划 2018KW-006
- DOI：
  中图分类号：
- 纸质出版：2020
- 稿件说明：
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贺飞龙, 蒋林, 刘新闯, 山蕊, 王昱, 吴皓月. 一种提前终止单元划分的帧内预测动态可重构实现[J]. 微电子学与计算机, 2020, 37(2): 15-19.

HE Fei-long, JIANG Lin, LIU Xin-chuang, et al. An intra-prediction dynamic reconfigurable implementation of early termination unit partitioning[J]. 2020, 37(2): 15-19.
贺飞龙, 蒋林, 刘新闯, 山蕊, 王昱, 吴皓月. 一种提前终止单元划分的帧内预测动态可重构实现[J]. 微电子学与计算机, 2020, 37(2): 15-19. DOI：

HE Fei-long, JIANG Lin, LIU Xin-chuang, et al. An intra-prediction dynamic reconfigurable implementation of early termination unit partitioning[J]. 2020, 37(2): 15-19. DOI：

摘要

针对专用硬件实现高效视频编码(High Efficiency Video Coding，HEVC)帧内预测算法资源占用大，且硬件资源不能重复利用、灵活性差的问题.提出一种可重构的视频阵列处理器，能够根据当前视频序列的特点进行帧内预测算法的动态映射.首先，分析HEVC帧内预测算法的特点和重构的可行性，以提前终止编码块划分的阈值作为处理器进行硬件重构的依据.其次，以计算出来的参数驱动可重构阵列处理器进行硬件重构.最后，在重构的阵列处理器上进行帧内预测算法映射.通过在4×4的可重构阵列上进行Planar和DC两种预测模式实现，结果表明：与专用硬件实现方法相比资源减少了65%，与多核处理器实现方法相比延时降低了32%.

Abstract

The High Efficiency Video Coding (HEVC) intra prediction algorithm for the dedicated hardware has a large resource occupation

and the hardware resources cannot be reused and the flexibility is poor. A reconfigurable video array processor is proposed

which can dynamically map the intra prediction algorithm according to the characteristics of the current video sequence. Firstly

the characteristics of HEVC intra prediction algorithm and the feasibility of reconstruction are analyzed. The threshold of early termination of coding block partition is determined as the basis for processor hardware reconstruction. Second

the reconfigurable array processor is driven by the calculated parameters for hardware reconstruction. Finally

intra prediction algorithm mapping is performed on the reconstructed array processor. By performing Planar and DC prediction mode experiments on a 4×4 reconfigurable array

the results show that the resource is reduced by 65% compared with the dedicated hardware implementation method

and the latency is reduced by 32% compared with the multi-core processor implementation.

关键词

Keywords

references

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GUO L, WANG X D, XU B W, et al. Fast algorithm for intra prediction mode decision and coding unit partitioning based on HEVC[J]. Journal of Computer Applications, 2018, 38(4): 1157-1163. DOI: 1157

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谢晓燕, 徐卫芳, 刘帆. HEVC帧内预测Planar和DC模式算法的并行化设计[J].电视技术, 2015, 39(5):4-8. DOI: 4

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张雪婷, 蒋林, 邓军勇, 等.可重构视频阵列处理器中全局控制器的设计与实现[J].微电子学与计算机, 2017, 34(11):75-79. DOI: 75

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