一种面向多处理器互连的高速串行传输系统设计

许晋彰; 景乃锋; 蒋剑飞

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一种面向多处理器互连的高速串行传输系统设计

更新时间：2026-09-04

- 一种面向多处理器互连的高速串行传输系统设计
- Design of high speed serial transmission system for multiprocessor interconnects
- 微电子学与计算机 2020年37卷第8期页码：16-20
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
  
  国家自然科学基金项目 61176037
- DOI：
  中图分类号：
- 纸质出版：2020
- 稿件说明：
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许晋彰, 景乃锋, 蒋剑飞. 一种面向多处理器互连的高速串行传输系统设计[J]. 微电子学与计算机, 2020, 37(8): 16-20.

XU Jin-zhang, JING Nai-feng, JIANG Jian-fei. Design of high speed serial transmission system for multiprocessor interconnects[J]. 2020, 37(8): 16-20.
许晋彰, 景乃锋, 蒋剑飞. 一种面向多处理器互连的高速串行传输系统设计[J]. 微电子学与计算机, 2020, 37(8): 16-20. DOI：

XU Jin-zhang, JING Nai-feng, JIANG Jian-fei. Design of high speed serial transmission system for multiprocessor interconnects[J]. 2020, 37(8): 16-20. DOI：

摘要

为了应对大数据量实时处理，解决处理器间通信带宽瓶颈.采用自主设计的混合多FPGA平台搭建了面向新型RISC-V处理器互连的高速串行传输系统，通过对互连接口的改进，实现了单通道4倍传输速率的提升.实验表明，该系统总吞吐率可达300 Gbps，单通道速率最高可达25 Gbps，支持的互连链路大于40路，传输误码率低于1E-11，能够满足高带宽、高可靠性传输需求，同时极大地减少了IO管脚数量.最后，基于该系统，在相同速率下对比和评估了3种高速串行协议的实现情况，为传输效率提升和系统优化提供帮助.

Abstract

In order to deal with the real-time processing of large data volume

and to solve the communication bandwidth bottleneck between processors

a high-speed serial transmission system for the interconnection of new RISC-V processors was built by self-developed hybrid multi-FPGA platform. It has achieved a single-channel 4x transmission rate improvement. Experiments show that the total throughput rate of the system can reach 300 Gbps

the single channel rate can reach 25 Gbps

the supported interconnect links are greater than 40

and the transmission error rate is less than 1E -11

which can meet most high-bandwidth and high-reliability transmission requirements

greatly reducing the number of IO pins. Finally

based on this system

at the same rate

compare and evaluate the implementation of three high-speed serial protocols

To help improve transmission efficiency and system optimization.

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Keywords

references

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