This paper proposes a design scheme of digital upconverter (DUC) embedded in 8GS/s-14bit RF-DAC. The scheme is implemented by ASIC

which can get the output signal with sampling frequency up to 8GHz and provide interpolation factors 2

4

8

16 upconversion function

respectively. Based on the CORDIC algorithm

a 16-channel time-domain interleaved numerically controlled oscillator (NCO) structure is proposed

and an interpolation filter set is realized by using a full half-band filter (HB-FIR) folding structure cascade. Based on the 40nm CMOS process

the RTL-level design and GDSII layout design are completed and embedded in the 8GS/s-14bit RF-DAC to complete the circuit design and verification of the hybrid SOC. The test results show that the design can achieve the design goal at 500 MHz working clock frequency. The layout area of the digital part is 2 551*2 580μm

the simulation power consumption is about 1 365.4 mW. And the film is tested in 40 nm CMOS process

The results show that the chip design can achieve the preset target

and in the mode of interpolation 16

the power consumption of the digital part of the chip is measured to be 1 250 mW

which is in line with the design expectations.