锗硅外延工艺优化对28 nm PMOS器件性能的改善

李帅; 蔡小五; 隋振超

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锗硅外延工艺优化对28 nm PMOS器件性能的改善

更新时间：2026-09-04

- 锗硅外延工艺优化对28 nm PMOS器件性能的改善
- Improvement of 28 nm PMOS device performance by SiGe EPI technology optimization
- 微电子学与计算机 2020年37卷第5期页码：28-32
- 作者机构：
  
  1. 中国科学院大学机构微电子学院,北京,100029
  2. 中国科学院机构微电子研究所,北京,100029
  3. 中芯国际集成电路制造有限公司,上海,201210
- 作者简介：
- 基金信息：
  
  国家自然科学基金 61874135
- DOI：
  中图分类号：
- 纸质出版：2020
- 稿件说明：
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李帅, 蔡小五, 隋振超. 锗硅外延工艺优化对28 nm PMOS器件性能的改善[J]. 微电子学与计算机, 2020, 37(5): 28-32.

LI Shuai, CAI Xiao-wu, SUI Zhen-chao. Improvement of 28 nm PMOS device performance by SiGe EPI technology optimization[J]. 2020, 37(5): 28-32.
李帅, 蔡小五, 隋振超. 锗硅外延工艺优化对28 nm PMOS器件性能的改善[J]. 微电子学与计算机, 2020, 37(5): 28-32. DOI：

LI Shuai, CAI Xiao-wu, SUI Zhen-chao. Improvement of 28 nm PMOS device performance by SiGe EPI technology optimization[J]. 2020, 37(5): 28-32. DOI：

摘要

在28 nm CMOS技术节点，锗硅技术在器件沟道产生压应力可以提高PMOS电学性能.在选择性锗硅外延工艺基础上对锗含量进行细化阶梯分布，此阶梯式分布能避免因锗含量过高产生位错而进一步提高总体应力效果.通过研究发现，薄膜堆叠层的厚度和锗元素浓度是影响器件性能的重要因素，实验对堆叠层厚度和锗浓度同时改变比单独改变一种影响因素获得的器件性能更好，器件的饱和电流和漏电流的性能(Idsat-Ioff)可以提高7%，同时，器件阈值电压和饱和电流的性能(Vtsat-Idsat)、器件阈值电压和漏电流(Vtsat-Ioff)性能、漏致势垒降低(DIBL)效应也有相应的改善.

Abstract

In the 28nm CMOS technologynode

Silicon germanium technology produces compressive stress in the device channel to improve PMOS electrical performance.Germanium are doped in stepped way based on selective silicon germanium epitaxial process

it can avoid the occurrence of dislocations due to higher dose of germanium and further improve the overall stress effect.Besides research

The thickness of the thin film stack and the concentration of germanium are important factors affecting device performance.Simultaneously changing the thickness of the stacked layer and the germanium concentration is better than the performance ofdevice obtained by separately changing one of the influencing factors.On state current and off state current performance(Idsat-Ioff) can improve 7%

simultaneously

Vtsat-Idsat performance

Vt-Ioff performance and DIBL also have obvious improvement.

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references

MENG X, LI Q, HUANG J, et al. Method of improving dislocation for SiGe EPI process[C]//2015 China Semiconductor Technology International Conference. Shanghai, IEEE, 2015: 1-3.

WANG L L, ZHANG J C, JIANG Y L. Optimization of Ni (Pt)/Si-cap/SiGe silicidation for pMOS source/drain contact[J]. IEEE Transactions on Electron Devices, 2017, 64(5): 2067-2071. DOI: 2067

施敏.半导体器件物理[M]. 3版.西安:西安交通大学出版社, 2008.

BAUDOT S, ANDRIEU F, WEBER O, et al. Fully depleted strained silicon-on-insulator p-MOSFETs with recessed and embedded silicon-germanium source/drain[J]. IEEE Electron Device Letters, 2010, 31(10): 1074-1076. DOI: 1074

KOMODA T, OISHI A, SANUKI T, et al. Mobility improvement for 45nm node by combination of optimized stress and channel orientation design[C]//IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. New York, IEEE, 2004: 217-220.

PARK M S, LEE K T, KANG C Y, et al. The Effect of a Si Capping Layer on RF Characteristics of High- k Metal Gate SiGe Channel pMOSFETs[J]. IEEE Electron Device Letters, 2010, 31(10): 1104-1106. DOI: 1104

OUYANG Q, CHEN X D, MUDANAI S, et al. Two-dimensional bandgap engineering in a novel Si-SiGe pMOSFET with enhanced device performance and scalability[C]//2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No. 00TH8502). Seattle, WA, USA, IEEE, 2000: 151-154..

张汝京.纳米集成电路制造工艺[M]. 2版.北京:清华大学出版社, 2017.

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