一种高能效的比特重排序及扩展FastTag Cache 单粒子效应容错方法

梁贤赓; 高瑛珂; 华更新

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一种高能效的比特重排序及扩展FastTag Cache 单粒子效应容错方法

更新时间：2026-09-04

- 一种高能效的比特重排序及扩展FastTag Cache 单粒子效应容错方法
- A high-efficiency cache SEU fault tolerance method using bit selective placement and extended-FastTag
- 微电子学与计算机 2020年37卷第9期页码：37-42
- 作者机构：
  
  北京控制工程研究所,北京,100094
- 作者简介：
- 基金信息：
  
  北京市科学技术委员会资助项目 Z191100004619003
- DOI：
  中图分类号：
- 纸质出版：2020
- 稿件说明：
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梁贤赓, 高瑛珂, 华更新. 一种高能效的比特重排序及扩展FastTag Cache 单粒子效应容错方法[J]. 微电子学与计算机, 2020, 37(9): 37-42.

LIANG Xian-geng, GAO Ying-ke, HUA Geng-xin. A high-efficiency cache SEU fault tolerance method using bit selective placement and extended-FastTag[J]. 2020, 37(9): 37-42.
梁贤赓, 高瑛珂, 华更新. 一种高能效的比特重排序及扩展FastTag Cache 单粒子效应容错方法[J]. 微电子学与计算机, 2020, 37(9): 37-42. DOI：

LIANG Xian-geng, GAO Ying-ke, HUA Geng-xin. A high-efficiency cache SEU fault tolerance method using bit selective placement and extended-FastTag[J]. 2020, 37(9): 37-42. DOI：

摘要

空间应用处理器Cache一直是抗辐射加固设计的薄弱环节，造成国产加固器件的Cache不能在轨应用，大大制约了空间应用处理器的性能.Cache中保存着处理器当前使用最频繁的指令和数据，Cache加固的效果，直接决定了空间应用处理器的抗单粒子翻转(SEU)能力.处理器缓存标签阵列(Cache Tag Array)是Cache系统的核心，传统SEC仅能对Tag单位错误进行纠正，邻位双错会引起误纠正，在组相连和全相连的Cache中会引起较大的面积功耗开销.本文设计了结合比特重排序技术和扩展FastTag技术的高能效Cache Tag容错方法，具有三方面特点：(1)扩展传统FastTag技术在写回Cache应用的局限性；(2)冗余码率与SEC一样的条件下，降低邻位双错的误纠正概率；(3)和传统SEC方法相比，降低容错带来的面积功耗开销.经过仿真与评估，与传统SEC容错设计相比，能效比得到提高.可以将邻位双错检测率提高70%左右；面积开销降低12.1%；功耗开销降低47.6%；关键路径延迟降低0.2 ns.

Abstract

Cache in the space application processor has always been a vulnerable spot in radiation-hardened design

which leads the Cache of domestic devices cannot be used in orbit. Cache stores the frequently used instructions and data

and the radiation-hardened effect of Cache directly determines the capability of anti-SEU of the space application processor. Tag Array is an important part in Cache

traditional SEC method used in which can only correct single bit error

and double adjacent bits error may cause false correction. Whats more

it will cause a large area and power overhead when used in set-associative and full-associative Cache. This paper designs an energy-efficient Cache Tag fault-tolerant method

which combines bit selective placement strategy and extended-FastTag. The proposed has three characteristics: (1) Extend the traditional FastTag technique to write-back Cache. (2) Improve the detection rate of double adjacent error with the same code redundancy rate compared to traditional SEC. (3) Reduce the area and power overhead caused by fault tolerance compared to traditional SEC. By simulation and evaluation

the energy efficiency ratio is improved compared to the traditional SEC method. The adjacent double error detection rate can be increased about 70%

and the area overhead is reduced by 12.1%

and the power consumption overhead is reduced by 47.6%

and the critical path delay is reduced about 0.2ns.

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references

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