上海交通大学 电子信息与电气工程学院,上海,200240
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李瑞, 蒋剑飞, 王琴. 一种基于三态反相器的高精度时间放大器[J]. 微电子学与计算机, 2020, 37(8): 43-48.
LI Rui, JIANG Jian-fei, WANG Qin. A high precision time-difference amplifier based on tri-state inverter[J]. 2020, 37(8): 43-48.
传统的基于三态反相器设计的时间放大器(TDA)具有电路复杂度低、对电压余度和温度的影响不敏感的特点,但该结构的时间分辨率低,增益误差大,应用范围相对较窄.本文提出一种改进的时间放大器结构,通过重新设计延迟链控制信号产生电路以实现高精度增益的要求.基于40 nm CMOS工艺进行Spectre仿真结果表明,本文提出的TDA结构不仅具有稳定可控的增益(增益误差保持在±4%以下)和高时间分辨率(380 fs),而且输入范围得到进一步提升.
The traditional three-state inverter based time-difference amplifier (TDA) has the characteristics of low circuit complexity
insensitivity to voltage margin and temperature
but the structure has low time resolution
large gain error and relatively narrow application range. An improved TDA structure that achieves high-precision gain by redesigning the delay chain control signal generation circuit is presented in this paper.Measurement results of Spectre based on 40 nm CMOS process show that the proposed TDA not only has stable and controllable gain (gain error is less than ±4%) and high time resolution (up to 380 fs)
but the input range is further improved.
CHEN H, ZHANG Y, LI D D. A low nonlinearity, missing-code free time-to-digital converter based on 28-nm FPGAs with embedded bin-width calibrations [J]. IEEE Transactions on Instrumentation and Measurement, 2017, 66(7): 1912-1921. DOI: 1912
CAO Y, COCK W D, STEYAERT M, et al. 1-1-1 MASH Delta-Sigma time-to-digital converters with 6 ps resolution and third-order noise-shaping [J]. IEEE Journal of Solid-State Circuits, 2012, 47(9): 2093-2106. DOI: 2093
LEE S, SEO Y, SUH Y, et al. A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18μm CMOS [C] // IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2010: 482-483.
KIM B, KIM H, KIM C H. An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier [C] // IEEE Custom Integrated Circuits Conference. San Jose, CA, USA. 2015: 1-4.
YU W, KIM K, CHO S. A0.22 ps rms integrated noise 15 MHz bandwidth fourth-order ΔΣ time-to-digital converter using time-domain error-feedback filter [J]. IEEE Journal of Solid-State Circuits, 2015, 50(5): 1251-1262. DOI: 1251
HEO M, KWON D, LEE M. Low-power programmable high gain time difference amplifier with regeneration time control [J]. Electronics Letters, 2014, 50(16): 1129-1131. DOI: 1129
CHIU P, LIU M, TANG Q, et al. A 2.1 pJ/bit, 8 Gb/s ultra-low power in-package serial link featuring a time-based front-end and a digital equalizer [C] // IEEE Asian Solid-State Circuits Conference. Tainan, Taiwan, China. 2018: 187-190.
LEE M, ABIDI A A. A 9b, 1.25ps resolution coarse-fine time-to-digital converter in 90nm CMOS that amplifies a time residue [C] // IEEE Symposium on VLSI Circuits. Kyoto, Japan. 2007: 168-169.
LYU Y X, FENG J H, YE H F, et al. All-digital synchronous 2 × time-difference amplifier based on time register [J]. Electronics Letters, 2017, 53(16): 1102-1104. DOI: 1102
NARAGHI S, COURCY M, FLYNN M P. A 9-bit, 14 μW and 0.06 mm2 pulse position modulation ADC in 90 nm digital CMOS [J]. IEEEJournal of Solid-State Circuits, 2010, 45(9):1870-1880. DOI: 1870
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