基于FPGA的卷积神经网络硬件加速器设计空间探索研究

郭谦; 贺光辉

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基于FPGA的卷积神经网络硬件加速器设计空间探索研究

更新时间：2026-09-04

- 基于FPGA的卷积神经网络硬件加速器设计空间探索研究
- Research on design space exploration of FPGA-based convolutional neural network hardware accelerator
- 微电子学与计算机 2020年37卷第8期页码：66-71
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
  
  上海航天联合基金 USCAST2019-28
- DOI：
  中图分类号：
- 纸质出版：2020
- 稿件说明：
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郭谦, 贺光辉. 基于FPGA的卷积神经网络硬件加速器设计空间探索研究[J]. 微电子学与计算机, 2020, 37(8): 66-71.

GUO Qian, HE Guang-hui. Research on design space exploration of FPGA-based convolutional neural network hardware accelerator[J]. 2020, 37(8): 66-71.
郭谦, 贺光辉. 基于FPGA的卷积神经网络硬件加速器设计空间探索研究[J]. 微电子学与计算机, 2020, 37(8): 66-71. DOI：

GUO Qian, HE Guang-hui. Research on design space exploration of FPGA-based convolutional neural network hardware accelerator[J]. 2020, 37(8): 66-71. DOI：

摘要

为了解决基于FPGA的卷积神经网络硬件加速器资源分配的问题，提出一种基于细粒度流水线架构的设计空间探索方法.为了提高吞吐率，该方法主要使用了三种技术：1)通过对DSP进行多阶段分配，实现各级流水线平衡；2)利用可调节的中间值缓存，协调BRAM和DDR带宽资源；3)利用深度可分解卷积替换部分卷积层，减少网络整体计算量.为了验证提出的设计空间探索方法，在ZC-706FPGA上实现了YOLO2-tiny网络，结果表明与同类设计相比，本设计的吞吐率与能效比高，整体延时低.

Abstract

In order to solve the problem of allocating resourcesforFPGA-based convolutional neural network hardware accelerator

a design space exploration method based on fine-grained pipeline architecture is proposed. In order to improve throughput

the method mainly uses three technologies: 1) achieve multi-stage allocation of DSP to balance the pipeline; 2) introduce adjustable intermediate result buffer to coordinate BRAM and DDR bandwidth resources; 3) utilize the depth decomposable convolution to replace part of the convolutional layers to reduce the overall computation of the network. In order to verify the proposed design space exploration method

the YOLO2-tiny network is implemented on the ZC-706 FPGA. Compared with the similar design

the results show thatthethroughput and energy efficiencyofthedesign are relatively higher

and the overall latency is shorter.

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references

MOTAMEDI M, GYSEL P, AKELLA V, et al. Design space exploration of FPGA-based deep convolutional neural networks[C]//2016 Asia and South Pacific Design Automation Conference. Macao: IEEE, 2016: 575-580.

ZHANG C, LI P, SUN G, et al. Optimizing fpga-based accelerator design for deep convolutional neural networks[C]//2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. Monterey: ACM/SIGDA, 2015: 161-170.

ZHANG S, HE G, CHEN H B, et al. Scale adaptive proposal network for object detection in remote sensing images[J].IEEE Geoscience and Remote Sensing Letters, 2019, 16(6): 864-868. DOI: 864

ZHANG X, WANG J, ZHU C, et al. DNNBuilder: an automated tool for building high-performance DNN hardware accelerators for FPGAs[C]//2018 IEEE/ACM International Conference on Computer-Aided Design. San Diego: IEEE, 2018: 1-8.

YU J, GUO K, HU Y, et al. Real-time object detection towards high power efficiency[C]//2018 Design, Automation % Test in Europe Conference % Exhibition. Dresden: IEEE, 2018: 704-708.

HOWARD A G, ZHU M, CHEN B, et al. Mobilenets: Efficient convolutional neural networks for mobile vision applications[J].arXiv preprint arXiv: 1704.04861, 2017.

WAI Y J, BIN MOHD YUSSOF Z, BIN SALIM S I, et al. Fixed point implementation of tiny-yolo-v2 using opencl on fpga[J].International Journal of Advanced Computer Science and Applications, 2018, 9(10): 506-512. DOI: 506

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