抗内存攻击的加密芯片双重动态混淆策略

景凤池; 张金艺

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抗内存攻击的加密芯片双重动态混淆策略

更新时间：2026-09-04

- 抗内存攻击的加密芯片双重动态混淆策略
- Anti-memory attack encryption chip dual dynamic obfuscation strategy
- 微电子学与计算机 2020年37卷第5期页码：75-81
- 作者机构：
  
  1. 上海大学微电子研究与开发中心,上海,200444
  2. 上海大学特种光纤与光接入网重点实验室,上海,200444
- 作者简介：
- 基金信息：
  
  十三五国家重点研发计划项目 2017TFB0403500
- DOI：
  中图分类号：
- 纸质出版：2020
- 稿件说明：
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景凤池, 张金艺. 抗内存攻击的加密芯片双重动态混淆策略[J]. 微电子学与计算机, 2020, 37(5): 75-81.

JING Feng-chi, ZHANG Jin-yi. Anti-memory attack encryption chip dual dynamic obfuscation strategy[J]. 2020, 37(5): 75-81.
景凤池, 张金艺. 抗内存攻击的加密芯片双重动态混淆策略[J]. 微电子学与计算机, 2020, 37(5): 75-81. DOI：

JING Feng-chi, ZHANG Jin-yi. Anti-memory attack encryption chip dual dynamic obfuscation strategy[J]. 2020, 37(5): 75-81. DOI：

摘要

目前，基于线性反馈移位寄存器(Linear Feedback Shift Register

LFSR)的动态混淆策略和测试授权策略是保护加密芯片免受扫描旁路攻击威胁的主流方法，然而存储在内存中的LFSR种子或测试授权密钥极易受到针对内存的攻击.针对此问题，从应对扫描旁路攻击和应对内存攻击两个角度出发，设计双重动态混淆架构并基于此架构构建双重动态混淆策略.其中，构建基于LFSR自更新模块的扫描链数据动态混淆策略以应对扫描旁路攻击；构建LFSR输出序列动态混淆策略以应对内存攻击.实验表明，相较于目前主流的安全扫描策略，双重动态混淆策略在不影响芯片可测试性的同时，可以使加密芯片免受扫描旁路攻击和内存攻击的威胁；在LFSR自更新模块位数为64位、插入混淆逻辑门中异或门和同或门数量各为8位的的情况下，面积开销为0.31%，攻击人员暴力破解双重动态混淆策略所需应用的测试向量至少为6.29×10个.

Abstract

At present

the dynamic obfuscation strategy based on the Linear Feedback Shift Register (LFSR) and the test authorization strategy are the mainstream methods to protect the encryption chip from the threat of side scan-based attack. However

the LFSR seed or test authorization key stored in memory is extremely vulnerable to the attack on memory. To solve this problem

a dual dynamic obfuscation architecture is designed and a dual dynamic obfuscation strategy is constructed based on the two perspectives of side scan-based attack and memory attack. Among them

a dynamic obfuscation strategy of scan chain data based on LFSR self-update module is constructed to deal with side scan-based attack. Build an LFSR output sequence dynamic obfuscation strategy against memory attack. Experiments show that compared with the current secure scan strategy

the dual dynamic obfuscation strategy can protect the encryption chip from side scan-based attack and memory attack without affecting the testability of the chip. The area overhead is 0.31% when the LFSR self-update module number is 64 bits

and the number of XOR and XNOR gates in obviating logic gates are 8 bits each

it would needapplied at least 6.29×1018 test vectors for the attacker to brute force the dual dynamic obfuscation strategy.

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Keywords

references

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