面向RISC-V指令集架构处理器的代码压缩技术

程战涛; 梁峰; 张国和

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面向RISC-V指令集架构处理器的代码压缩技术

更新时间：2026-09-04

- 面向RISC-V指令集架构处理器的代码压缩技术
- Code compression technology for processors based on RISC-V instruction set architecture
- 微电子学与计算机 2021年38卷第6期页码：13-19
- 作者机构：
  
  西安交通大学微电子学院,陕西,西安,710049
- 作者简介：
- 基金信息：
  
  国家自然科学基金资助项目 61474093陕西省自然科学基金资助项目 2020JM-006航空科学基金项目 20184370012
- DOI：
  中图分类号：
- 纸质出版：2021
- 稿件说明：
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程战涛, 梁峰, 张国和. 面向RISC-V指令集架构处理器的代码压缩技术[J]. 微电子学与计算机, 2021, 38(6): 13-19.

CHENG Zhan-tao, LIANG Feng, ZHANG Guo-he. Code compression technology for processors based on RISC-V instruction set architecture[J]. 2021, 38(6): 13-19.
程战涛, 梁峰, 张国和. 面向RISC-V指令集架构处理器的代码压缩技术[J]. 微电子学与计算机, 2021, 38(6): 13-19. DOI：

CHENG Zhan-tao, LIANG Feng, ZHANG Guo-he. Code compression technology for processors based on RISC-V instruction set architecture[J]. 2021, 38(6): 13-19. DOI：

摘要

针对嵌入式系统处理器代码量指数式增长带来的设计与验证难题，提出一种适用于RISC-V指令集架构处理器的Bitmask代码压缩技术.结合RISC-V指令集特点，设计了混合编码与分离字典相结合的Bitmask代码压缩算法; 在不影响处理器结构和Cache工作机制的基础上，设计精简的硬件解压缩单元，减小了嵌入式系统处理器所需的程序内存空间.采用面向RISC-V指令集的混合编码压缩指令格式，减小原始指令码的码字长度，改善了代码压缩率; 采用分离的两个字典结构，在不影响代码压缩率的前提下，减小了硬件解压缩延迟.结果表明，在RISC-V指令集架构上不增加过多硬件开销的情况下，代码压缩率平均为61.1%，大大减小了处理器所需的程序内存空间.

Abstract

Aiming at design and verification problems caused by the exponential growth of the code size in the embedded system processors

the Bitmask-based code compression technology for processors based on RISC-V instruction set architecture is presented. Based on the features of RISC-V instruction set

a Bitmask-based code compression algorithm combined with mixed encoding and separate dictionary is designed. Without affecting the processor structure and Cache working mechanism

a simple and efficient hardware decompression unit is designed to reduce the program memory space required by the embedded system processor. Mixed encoding format for RISC-V instruction set is used to reduce the length of the original instruction

which improves the code compression rate. Besides

two separated dictionaries are used to obtain a small hardware decompression delay without affecting the code compression rate. The experimental results show that the code compression ratio is 61.1% on average without much hardware overhead on the RISC-V instruction set architecture

which greatly reduces the program memory space required by the processor.

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references

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